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* Merge http://git.denx.de/u-boot-sunxiTom Rini2014-10-26-9/+33
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| * mmc: sunxi: Add support for sun8i (A23)Chen-Yu Tsai2014-10-24-1/+1
| | | | | | | | | | | | | | | | | | | | The Allwinner A23 SoC has reset controls like the A31 (sun6i). The FIFO address is also the same as sun6i. Re-use code added for sun6i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: When we've both mmc0 and mmc2, detect from which one we're bootingHans de Goede2014-10-24-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're booting, and make that one "mmc dev 0" so that a single u-boot binary can be used for both the onboard eMMC and for external sdcards. When we're booting from mmc2, we make it dev 0 because that is where the SPL will load the tertiary payload (the actual u-boot binary in our case) from, see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add mmc card-detect functionalityHans de Goede2014-10-24-0/+21
| | | | | | | | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * ARM: sunxi-mmc: Add mmc support for sun6i / A31Hans de Goede2014-10-24-4/+7
| | | | | | | | | | | | | | | | | | | | | | The mmc hardware on sun6i has an extra reset control that needs to be de-asserted prior to usage. Also the FIFO address is different. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: use setbits_le32 for reset control, drop obsolete changes, rewrite different FIFO address handling, add commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * mmc: sunxi: add SDHC support for sun6i/sun7i/sun8iWills Wang2014-10-24-0/+3
| | | | | | | | | | | | | | Allwinner A20/A23/A31's SD/MMC host support SDHC High Capacity feature. Signed-off-by: Wills Wang <wills.wang.open@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2014-10-26-5/+10
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | Fix a trivial conflict over adding <dm.h> Conflicts: arch/arm/cpu/armv7/omap3/board.c Signed-off-by: Tom Rini <trini@ti.com>
| * | dm: omap: gpio: Support driver modelSimon Glass2014-10-23-5/+10
| |/ | | | | | | | | | | | | | | | | | | | | | | Add driver model support to this driver, while retaining support for the legacy system. Driver model GPIO support is enabled with CONFIG_DM_GPIO as usual. Since gpio_is_valid() no longer exists, we can use the -EINVAL error returned from gpio_request(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
* | mmc: bcm2835_sdhci: add missing includeJeroen Hofstee2014-10-25-0/+1
| | | | | | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | tegra: make local functions staticJeroen Hofstee2014-10-25-1/+2
| | | | | | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | sdhci: make local functions staticJeroen Hofstee2014-10-25-3/+3
|/ | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2014-10-23-1/+1
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| * mmc: Tegra: Fix timeout issue seen on certain eMMC partsMarcel Ziswiler2014-10-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During rigorous testing of our latest update infrastructure I came across quite consistent timeouts on certain eMMC parts (e.g. Hynix H26M21001ECR) when writing big (e.g. in excess of 400 MB) file system images: MMC write: dev # 0, block # 40960, count 944128 ... mmc_send_cmd_bounced: MMC Timeout Interrupt status 0x00000001 Interrupt status enable 0xdfff003b Interrupt signal enable 0xdfff0002 Present status 0x01870106 mmc write failed Comparing the various data sheets I came across the following timeout specification: Secure Erase/TRIM Timeout=300ms*2*10=6000ms Unfortunately empirical testing still failed albeit much more rarely. Increasing the timeout to 8000ms made it finally disappear entirely. This patch allows us writing various eMMC parts without seeing any further issues. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | arm: marvell: Move arch/kirkwood.h to arch/soc.hStefan Roese2014-10-23-1/+1
| | | | | | | | | | | | | | | | | | This move makes is possible to use this header not only from kirkwood platforms but from all Marvell mvebu platforms. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
* | dm: exynos: Make sure that GPIOs are requestedSimon Glass2014-10-22-1/+6
|/ | | | | | | | | | With driver model GPIOs must be requested before use. Make sure this is done correctly. (Note that the soft SPI part of universal is omitted, since this driver is about to be replaced with a driver-model-aware version) Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-10-11-25/+111
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| * Merge branch 'topic/arm/socfpga-20141006' of git://git.denx.de/u-boot-socfpgaTom Rini2014-10-06-12/+27
| |\ | | | | | | | | | | | | | | | | | | | | | | | | Fix a trivial conflict in dw_mmc.c after talking with Marek. Conflicts: drivers/mmc/dw_mmc.c Signed-off-by: Tom Rini <trini@ti.com>
| | * arm: socfpga: mmc: Pick the clock from clock managerPavel Machek2014-10-06-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the SoCFPGA MMC stub pick clock via the clock manager frequency accessors instead of hard-coding the frequency. Also fix calloc() misuse. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| | * mmc: dw_mmc: cleanupsPavel Machek2014-10-06-12/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dw_mmc driver was responding to errors with debug(). Change that to prinf()/puts() respectively so that any errors are immediately obvious. Also adjust english in comments. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Acked-by: Chin Liang See <clsee@altera.com>
| * | dw_mmc: cleanupsPavel Machek2014-10-03-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | dw_mmc driver was responding to errors with debug(). Change that to prinf so that any errors are immediately obvious. Also adjust english in comments. Signed-off-by: Pavel Machek <pavel@denx.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | mmc: Fix mmc bus widthMario Schuknecht2014-10-03-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After setting the bus width, the extended CSD register is read. Some selected fields are compared with previously read extended CSD register fields. In this comparison the EXT_CSD_ERASE_GROUP_DEF field is compared. But this field is previously written under certain circumstances. And then the comparison fails. Only compare read-only fields. Therefore compare field EXT_CSD_HC_WP_GRP_SIZE instead of field EXT_CSD_ERASE_GROUP_DEF. Signed-off-by: Mario Schuknecht <mario.schuknecht@dresearch-fe.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | mvebu_mmc: Driver additionMario Schuknecht2014-10-03-1/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In function mvebu_mmc_write notice command timeout. It is possible that a command is done, but a timeout occurred. Enable timeout in set bus function. Set window registers. Without that I could not use the driver on a Kirkwood 88F6282 SoC. Set high capacity and 52MHz driver feature. Signed-off-by: Mario Schuknecht <mario.schuknecht@dresearch-fe.de> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | mmc: restore capacity when switching to partition 0Peter Bigot2014-10-03-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The capacity and lba for an MMC device with part_num 0 reflects the whole device. When mmc_switch_part() successfully switches to a partition, the capacity is changed to that partition. As partition 0 does not physically exist, attempts to switch back to the whole device will indicate an error, but the capacity setting for the whole device must still be restored to match the partition. Signed-off-by: Peter A. Bigot <pab@pabigot.com> Tested-by: Tom Rini <trini@ti.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * | mmc: fix ERASE_GRP_DEF handlingHannes Petermaier2014-10-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if we set manually this bit on the eMMC card using mmc_switch(...), we also have to set it within our (before read) internal structure 'ext_csd'. Otherwise following checks on this will fail. Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
| * | mmc: set correct block size value in bfin sdh driverSonic Zhang2014-10-03-3/+4
| |/ | | | | | | | | | | | | | | Wait data transfer till the data end bit other than the data block end bit is set. Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | samsung: Enable device tree for s5p_goniSimon Glass2014-10-08-2/+0
|/ | | | | | | | | Change this board to add a device tree. This also adds a pinmux header file although it is not used as yet. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* cosmetic: replace MIN, MAX with min, maxMasahiro Yamada2014-09-24-1/+1
| | | | | | | The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kconfig: add blank Kconfig filesMasahiro Yamada2014-09-24-0/+0
| | | | | | | | This would be useful to start moving various config options. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* ls102xa: esdhc: Add esdhc support for LS102xAWang Huan2014-09-08-2/+2
| | | | | | | | | | | For LS1, esdhc is big-endian IP. Accessing the registers should be in big-endian mode. So we use esdhc_read32() to read Host controller capabilities register for LS1. For LS1, when using CMD12, cmdtype need to be set to ABORT, otherwise, next read command will hang. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* socfpga: cleanup socfpga_dw_mmcPavel Machek2014-08-30-4/+4
| | | | | | | Cleanups as suggested by wd on mailing list. Signed-off-by: Pavel Machek <pavel@denx.de> Acked-by: Chin Liang See <clsee@altera.com>
* socfpga: fix clock manager register definitionPavel Machek2014-08-29-2/+2
| | | | | | | | | Structure defining clock manager hardware was wrong, leading to wrong registers being accessed and hang in MMC init. This fixes structure to match hardware. Signed-off-by: Pavel Machek <pavel@denx.de>
* MMC: atmel_mci: enable high speed mode supportBo Shen2014-08-01-1/+6
| | | | | | | | If the MCI IP version >= 0x300, it supports hight speed mode option, this patch enable it. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* MMC: atmel_mci: refactor setting the mode registerBo Shen2014-08-01-14/+42
| | | | | | | | The mode register is different between MCI IP version. So, according to MCI IP version to set the mode register. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc/dw_mmc: Fix clock divider calculation error for bypass modeChin Liang See2014-08-01-1/+4
| | | | | | | | | | | | To fix the clock divider calculation error when the controller clock same as the operating frequency. This is known as bypass mode. In this mode, the divider should be 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Mischa Jonker <mjonker@synopsys.com>
* mmc: s3c: Add SD driverMarek Vasut2014-08-01-0/+322
| | | | | | | | | | | | | | Implement SD driver for the S3C24xx family. This implementation is currently only capable of using the PIO transfers, DMA is not supported. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* bcm2835_sdhci: Add SDHCI_QUIRK_NO_HISPD_BIT flagLubomir Rintel2014-08-01-1/+1
| | | | | | | | Seems like the controller doesn't support the flag. None of the hi-speed cards I've tried could be read, while they successfully worked with the quirk enabled. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* ARM: kirkwood: add mvsdio driverDrEagle2014-08-01-0/+362
| | | | | | | | | This patch add Marvell kirkwood MVSDIO/MMC driver and enable it for Sheevaplugs and OpenRD boards. Signed-off-by: Gerald Kerma <drEagle@doukki.net> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-28-134/+7
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| * sunxi: Remove mmc DMA supportHans de Goede2014-07-06-134/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA code in sunxi_mmc.c is broken. mmc_trans_data_by_dma() allocates the dma descriptors on the stack, and then exits while the dma transfer is in progress, so the dma engine is reading stack memory which at that point may be re-used. So far we've gotten away with this by luck, but recent u-boot changes have shifted the stack start address by 16 bytes, which combined with dma alignment now exposes this problem. Since we end up just busy waiting for the dma engine anyway, this commit fixes things by simply removing the dma code, resulting in smaller bug-free code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | mmc: prevent some warnings with make W=1Jeroen Hofstee2014-07-18-4/+4
| | | | | | | | | | | | | | | | Add missing prototypes for global functions and make local functions static. cc: panto@antoniou-consulting.com Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | dirvers: mmc: use __weakJeroen Hofstee2014-07-18-11/+9
|/ | | | | use weak instead of alias to prevent some clang warnings. Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* includes: move openssl headers to include/u-bootJeroen Hofstee2014-06-19-1/+1
| | | | | | | | | | | | commit 18b06652cd "tools: include u-boot version of sha256.h" unconditionally forced the sha256.h from u-boot to be used for tools instead of the host version. This is fragile though as it will also include the host version. Therefore move it to include/u-boot to join u-boot/md5.h etc which were renamed for the same reason. cc: Simon Glass <sjg@chromium.org> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* mmc: free allocated memory on initialization errorsDarwin Rambo2014-06-12-2/+6
| | | | | | | | Cleanup to balance malloc/free calls. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: return meaningful error codes from mmc_select_hwpartStephen Warren2014-06-12-3/+4
| | | | | | | | | | | | Rather than just returning -1 everywhere, try to return something meaningful from mmc_select_hwpart(). Note that most other MMC functions don't do this, including functions called from mmc_select_hwpart(), so I'm not sure how effective this will be. Still, it's one less place with hard-coded -1. Suggested-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-02-103/+172
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| * mmc: s5p_sdhci: add the s5p_sdhci_core_init functionJaehoon Chung2014-05-16-25/+17
| | | | | | | | | | | | | | | | | | | | | | To reuse the code, added the s5p_sdhci_core_init function. Before applied this patch, didn't use the 8-bit mode at exynos baord. Because it didn't set "MMC_MODE_8BIT". Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * mmc: exynos_dw_mmc: enable the DDR modeJaehoon Chung2014-05-16-0/+1
| | | | | | | | | | | | | | | | | | Set the ddr mode capability by default. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * mmc: dw_mmc: support the DDR modeJaehoon Chung2014-05-16-2/+10
| | | | | | | | | | | | | | | | | | Support the DDR mode at dw-mmc controller Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * mmc: support the DDR mode for eMMCJaehoon Chung2014-05-16-3/+13
| | | | | | | | | | | | | | Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * mmc: remove the unnecessary define and fix the wrong bit controlJaehoon Chung2014-05-16-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Lukasz Majeski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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