| Commit message (Collapse) | Author | Age | Lines |
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As per JEDEC document JESD84-A441 (page 105) response for CMD7
(MMC_CMD_SELECT_CARD) response should be R1 instead of R1b. In uboot we
never take MMC to disconnected state and on powerup its always ideal
state which later goes to stand-by state.
from document footnote:
R1 while selecting from Stand-By State to Transfer State; R1b while
selecting from Disconnected State to Programming State.
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
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Remove u-boot build warnings for mx6q.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Modified MMC library for UHS-I command sequence
Added support to USDHC driver for UHS-I
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Need to send RCA when sending CMD13.
Cannot use print_size function when displaying card capacity
because it expects a 32 bit integer as input, while mmc->capacity
is a 64 bit integer. There is loss of information leading to incorrect
capacities being displayed for "mmcinfo" cmd. Changed it to simply
print the entire 64 bit integer, which is the number of bytes.
Signed-off-by: Tony Lin <tony.lin@freescale.com>
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Removed delay of 10 ms before each command. There should not be
a need to have this delay after the ENGR00156405 patch that polls
until card is not busy anymore before proceeding to next cmd.
Added poll on reset bits of controller after the bits are set to
wait until they clear before proceeding further.
Signed-off-by: Tony Lin <tony.lin@freescale.com>
Signed-off-by: Anish Trivedi <anish@freescale.com>
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The errata, not applicable to USDHC, causes ESDHC to shut off clock to
the card when auto-clock gating is enabled for commands with busy
signalling and no data phase. The card might require the clock to exit
the busy state, so the workaround is to disable the auto-clock gate
bits in SYSCTL register for such commands. The workaround also entails
polling on DAT0 bit in the PRSSTAT register to learn when busy state is
complete. Auto-clock gating is re-enabled at the end of busy state.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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After enabling boot partition on an eMMC using "mmc bootpart" command, the
partition configuration variable that is supposed to track this value on the
eMMC is not updated. This leads to stale and possibly inaccurate boot partition
number being printed when "mmcinfo" command is used, thereby confusing the user.
The fix is to update the part_config variable of mmc struct with the new value
that was just written to the eMMC.
Also removed condition that restricted boot_bus_width programming (for fastboot)
to eMMC with DDR support only. Now, even non-DDR capable eMMCs can be programmed
for fastboot (in SDR mode).
Signed-off-by: Anish Trivedi <anish@freescale.com>
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This patch will enhance mmc command.
1. Add erase command.
2. Abandon dev_no in mmc command. User need to switch slot with "mmc
dev" command.
3. Add mmc part switch command. Enhance partition switch support.
4. Add mmc bootpart. Boot partition support is more flexible.
Signed-off-by: Terry Lv <r65388@freescale.com>
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ROM requires DCD table instead of plugin to initialize DRAM if emmc fastboot
mode is to be used. Therefore, switched the DRAM script from plugin to
DCD table. The DCD table created is based on the following RVD script:
Arik_init_DDR3_528MHz_002.inc found at
http://compass.freescale.net/livelink/livelink?func=ll&objId=222928845
When fastboot mode is used by ROM, the MMC_BOOT register of USDHC does not
get reset when RSTA bit is set by uboot driver. Therefore, need to write 0
to it manually during driver init. This brings USDHC out of fastboot mode,
allowing normal communication with emmc to proceed in uboot.
Changed comments for DLL delay to be more accurate.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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New bit definitions in USDHC.
Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC
and USDHC.
Enabled DDR mode support in USDHC.
Created a config to customize target delay for DDR mode.
Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Use 528M DDR script
Disable L2 cache because rom enable L2 cache when use plug-in
Fix usdhc pad settings
Remove mac address hardcode
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Richard Zhu <r65037@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Anish Trivedi <anish@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
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On SD3 on MX50, there is an option to choose eSDHC or uSDHC controller.
By default eSDHC is selected. However, eSDHC shows some borderline timing
in SDR mode at 50 MHz, whereas uSDHC shows borderline timing in DDR mode
at 50 MHz. Therefore, add a compile time option to uboot for MX50 to
select uSDHC in SDR mode or eSDHC in DDR mode on SD3 port.
By default the compile time option, CONFIG_MX50_ENABLE_USDHC_SDR,
is commented out in the include/configs/mx50_<board>.h file to
select eSDHC with DDR mode enabled. Uncomment the define to select
uSDHC with only SDR mode enabled.
Also increased max frequency supported by ESDHC to 52 MHz instead
of 50 MHz.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Usually dll setup for eMMC4.4 DDR is required to polling SLV_LOCK status
bit. However the system hangs when polling for SLV_LOCK bit.
The temporary workaround is to force slave override mode to bypass it.
Signed-off-by: Terry Lv <r65388@freescale.com>
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We're following the following rules:
1. FSL copyright should be added for freescale added and modified files.
2. FSL copyright should go after existing copyrights.
3. For Duplicate FSL copyright, Our copyright will go after that also.
4. FSL copyright should not include personal names as part.
5. For only FSL copyright, "All rights reserved" is not mattered.
Signed-off-by: Terry Lv <r65388@freescale.com>
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MMC driver may wrongly regconize some 2GB eMMC as high capacity card.
This patch is picked from community.
A non-zero value of SEC_COUNT does not indicate that the card is sector
addressed. According to the MMC specification, cards
with a densitygreater than 2GiB are sector addressed.
Signed-off-by: Terry Lv <r65388@freescale.com>
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As in mx53 and lster socs, when using CMD12, cmdtype need to be set
to ABORT, otherwise, next read command will hang.
This is a software Software Restrictions in spec 29.7.8.
For pre-defined multi-block read operation,
i.e.,
The number of blocks to read has been defined by previous
CMD23 for MMC, or pre-defined number of blocks in CMD53
for SDIO/SDCombo, or whatever multi-block read without abort
command at card side, an abort command, either automatic
or manual CMD12/CMD52, is still required by ESDHCV2 after the
pre-defined number of blocks are done, to drive the internal
state machine to idle mode.
In this case, the card may not respond to this extra
abort command and ESDHCV2 gets Response Timeout.
It is recommended to manually send an abort command with
RSPTYP[1:0] both bits cleared.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Change mmc framework architecture.
Mainly for code clean and restructure.
Mainly merge our code with community code.
Based on commit 17b4c8e9eb30e3eb305baef98eb23325e61db592.
Signed-off-by: Terry Lv <r65388@freescale.com>
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1. As we can check DDR dynamically,
remove CONFIG_EMMC_DDR_MODE in mmc.c.
2. Add config CONFIG_EMMC_DDR_PORT_DETECT
config for some boards that only some board support DDR.
Signed-off-by: Terry Lv <r65388@freescale.com>
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On MX50 TO 1.0, DLL did not work in slave mode, so
slave override mode was used instead. Removed this
workaround, except for TO 1.0. Starting with TO 1.1,
the DLL in slave mode is working as expected.
Signed-off-by: Anish Trivedi <anish@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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Enable DDR mode on ESDHC controller and mmc library
Enable 8-bit support in mmc library
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Removed low voltage (1.8V) from supported voltage ranges.
Changed SD2_CMD pad setting to enable SD2 r/w in uboot.
Loaded env from booted device instead of SD1 always.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Enable boot partition in BOOT_CONFIG byte of EXT_CSD
Signed-off-by: Anish Trivedi <anish@freescale.com>
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Original uboot did not support sd1 and can only save environment
into sd0 even actually you're booting from sd1.
This patch adds the capability of saving environment into sd1
when you're booting from sd1.
Signed-off-by: Aisheng.Dong <b29396@freescale.com>
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System can not find MMC/SD card in SD
slot 1 when booting from Uboot.
Signed-off-by: Terry Lv <r65388@freescale.com>
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mmc can't read data whose size exceeds 32M.
Signed-off-by: Terry Lv <r65388@freescale.com>
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-Update eSDHC clock setting,
-Fix the GPT timer setting,
-Fix the boot option pars,
-Remove mdelay() function call to improve the performance
Signed-off-by:Jason Liu <r64343@freescale.com>
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MX28 U-BOOT enhancements.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add eMMC and eSD fast boot support.
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Brian Liu <b14843@freescale.com>
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Enable Ethernet and MMC boot support for imx28-evk
Signed-off-by: Frank Li <frank.li@freescale.com>
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Add a new config CONFIG_IMX_ESDHC_V1 for v1 support.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Fix MMC read/write failure due to eSDHC register definition wrong
Signed-off-by: Sammy He <r62914@freescale.com>
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In current u-boot design,
get_timer_masked is not correct and udelay is not accurate
when the time is less than 1000us.
Thus we need to use ipg clock source for accurate timer.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Some mmc card can't read and write from right offset.
Driver see these card as high capacity and use sector mode for them.
This will lead to read and write corrupt.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Misc changes for v2009.08 upgrade.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Signed-off-by: Terry Lv <r65388@freescale.com>
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U-BOOT upgrade from V2009.01 to V2009.08
Initial version for i.MX51 BBG board.
Support:
FEC, SPI, spi Nor Flash
Boot from spi nor flash and mmc/sd
Signed-off-by:Fred Fan <r01011@freescale.com>
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Enable cp command for MMC.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add MMC configs to mx35 3stack config file.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add FEC support for BBG2.
Signed-off-by: Terry Lv <r65388@freescale.com>
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BBG2: MMC boot support.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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This is a port of Linux driver for SDHC host controller hardware
found on Freescale's MX2 and MX3 processors. Uses new generic MMC
framework (CONFIG_GENERIC_MMC) and it looks like there are some
problems with a framework (at least on LE cpus). Some of these
problems are addressed in the following patches.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
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Because twl4030 now has its own device files, move and rename
twl4030_mmc_config.
twl4030_mmc_config initializes the twl4030 power setting to
the mmc device. Because it is in the twl4030 power domain, move
it out of drivers/mmc/omap3_mmc.c and into drivers/power/twl4030.c.
The function was renamed to twl4030_power_mmc_init because all
the functions in this file are to have the format
twl4030_power_<device>_<action>
In this case the suffix is mmc_init so
device : mmc
action : init
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Heiko Schocher <hs@denx.de>
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We need to switch back to 1-bit before initialization or SD 2.0 cards
will fail to send SCR if we've switched to 4-bit already.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
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This patch implements fdt_fixup_esdhc() function that is used to fixup
the device tree.
The function adds status = "disabled" propery if esdhc pins muxed away,
otherwise it fixups clock-frequency for esdhc nodes.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
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SCR & switch data are read from card as big-endian words and should be
converted to CPU byte order.
Signed-off-by: Yauhen Kharuzhy <jekhor@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Cards which are not compatible with SD 2.0 standard, may return response
for CMD8 command, but it will be invalid in terms of SD 2.0. We should
accept this case as admissible, just like Linux does.
Signed-off-by: Yauhen Kharuzhy <jekhor@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Now that response is a uint, we can drop all the casts.
Signed-off-by: Rabin Vincent <rabin@rab.in>
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The mmc code defines the response as an array of chars. However, it
access the response bytes both as (i) an array of four uints (with
casts) and (ii) as individual chars. The former case is used more
often, including by the driver when it assigns the response.
The char-wise accesses are broken on little endian systems because they
assume that the bytes in the uints are in big endian byte order.
This patch fixes this by changing the response to be an array of four
uints and replacing the char-wise accesses with equivalent uint-wise
accesses.
Signed-off-by: Rabin Vincent <rabin@rab.in>
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The generic MMC core uses direct long long divisions, which do not build
with ARM EABI toolchains. Use lldiv() instead, which works everywhere.
Signed-off-by: Rabin Vincent <rabin@rab.in>
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