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path: root/drivers/mmc/sdhci.c
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* mmc: sdhci: Add support for optional controller specific set_ios_post()Stefan Roese2017-01-25-0/+4
| | | | | | | | | | | | | | | Some SDHCI drivers might need to do some special controller configuration after the common clock set_ios() function has been called (speed / width configuration). This patch adds a call to the newly created function set_ios_port() when its configured in the host driver. This will be used by the Xenon SDHCI controller driver used on the Marvell Armada 3700 and 7k/8k ARM64 SoCs. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: Clear SDHCI_CLOCK_CONTROL before configuring the new valueStefan Roese2017-01-25-4/+2
| | | | | | | | | | | | | | | | | | | This patch completely clears the SDHCI_CLOCK_CONTROL register before the new value is configured instead of just clearing the 2 bits SDHCI_CLOCK_CARD_EN and SDHCI_CLOCK_INT_EN. Without this change, some clock configurations will lead to the "Internal clock never stabilised." error message on the Xenon SDHCI controller used on the Marvell Armada 3700 and 7k/8k ARM64 SoCs. The Linux SDHCI core driver also writes 0 to this register before the new value is configured. So this patch simplifies the driver a bit and brings the U-Boot driver more in-line with the Linux one. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: Distinguish between base clock and maximum peripheral frequencyStefan Herbrechtsmeier2017-01-23-16/+18
| | | | | | | | | | The sdhci controller assumes that the base clock frequency is fully supported by the peripheral and doesn't support hardware limitations. The Linux kernel distinguishes between base clock (max_clk) of the host controller and maximum frequency (f_max) of the card interface. Use the same differentiation and allow the platform to constrain the peripheral interface. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
* mmc: sdhci: fix NULL pointer access when host->ops is not setMasahiro Yamada2017-01-13-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Until recently, sdhci_ops was used only for overriding IO accessors. (so, host->ops was not set by any drivers except bcm2835_sdhci.c) Now, we have more optional callbacks, get_cd, set_control_reg, and set_clock. However, the code if (host->ops->get_cd) host->ops->get_cd(host); ... expects host->ops is set for all drivers. Commit 5e96217f0434 ("mmc: pic32_sdhci: move the code to pic32_sdhci.c") and commit 62226b68631b ("mmc: sdhci: move the callback function into sdhci_ops") added sdhci_ops for pic32_sdhci.c and s5p_sdhci.c, but the other drivers still do not (need not) set host->ops because all callbacks in sdhci_ops are optional. host->ops must be checked to avoid the system crash caused by NULL pointer access. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: sdhci: combine the Host controller v3.0 feature into one conditionJaehoon Chung2017-01-11-10/+7
| | | | | | It doesn't need to seperate the condition. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: remove the SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWERJaehoon Chung2017-01-11-3/+0
| | | | | | Ther is no usage anywhere. It doesn't need to maintain this bit. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: move the callback function into sdhci_opsJaehoon Chung2017-01-11-4/+4
| | | | | | | | callback function should be moved into sdhci_ops struct. Other controller can use these ops for controlling clock or their own specific register. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: change the set_ios return type from void to intJaehoon Chung2017-01-11-3/+2
| | | | | | To maintain consistency, set_ios type of legacy mmc_ops changed to int. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: remove the SDHCI_QUIRK_NO_CDJaehoon Chung2017-01-11-4/+2
| | | | | | | This quirk doesn't need anymore. It's replaced to get_cd callback function. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: pic32_sdhci: move the code to pic32_sdhci.cJaehoon Chung2017-01-11-6/+2
| | | | | | | | This code is used for only pic32_sdhci controller. To remove the "#ifdef", moves to pic32_sdhci.c. And use the get_cd callback function. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: remove the unused code about testing Card detectJaehoon Chung2017-01-11-11/+0
| | | | | | This code is dead code..There is no usage anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: disable the 8bit mode when host doesn't support itJaehoon Chung2017-01-11-3/+2
| | | | | | | | | | | | | Buswidth is depeneded on Hardware schematic. Evne though host can support the 8bit buswidth, if hardware doesn't support 8bit mode, it doesn't work fine. So the buswidth mode selection leaves a matter in each SoC drivers. On the contrary to this, hardware supports 8bit mode, but host doesn't support it. then controller has to disable the MMC_MODE_8BIT. (Host can check whether 8bit mode is supported or not, since V3.0) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: move some SDHCI related options to KconfigMasahiro Yamada2016-12-29-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While I moved the options, I also renamed them so that they are all prefixed with MMC_SDHCI_. This commit was created in the following steps. [1] Rename with the following command find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \ -type f -print | xargs sed -i -e ' s/CONFIG_MMC_SDMA/CONFIG_MMC_SDHCI_SDMA/g s/CONFIG_BCM2835_SDHCI/CONFIG_MMC_SDHCI_BCM2835/g s/CONFIG_KONA_SDHCI/CONFIG_MMC_SDHCI_KONA/g s/CONFIG_MV_SDHCI/CONFIG_MMC_SDHCI_MV/g s/CONFIG_S5P_SDHCI/CONFIG_MMC_SDHCI_S5P/g s/CONFIG_SPEAR_SDHCI/CONFIG_MMC_SDHCI_SPEAR/g ' [2] create the Kconfig entries in drivers/mmc/Kconfig [3] Move the options by the following command tools/moveconfig.py -y MMC_SDHCI_SDMA MMC_SDHCI_BCM2835 \ MMC_SDHCI_KONA MMC_SDHCI_MV MMC_SDHCI_S5P MMC_SDHCI_SPEAR [4] Sort drivers/mmc/Makefile for readability Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: assign to clk_mul when host version is upper than SD3.0Jaehoon Chung2016-10-28-3/+5
| | | | | | To prevent the wrong value check the SD version. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: fix the "misaligned operation at range" for cacheJaehoon Chung2016-10-28-0/+1
| | | | | | | | This pathc is fixed the below thing. If misaligned the cache range, Just flush to CACHLINE_SIZE. "CACHE: Misaligned operation at range [7ae55b00, 7ae55b08]" Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: use the generic error numberJaehoon Chung2016-10-10-6/+6
| | | | | | | Use the generic error number instead of meaningless value. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mmc: sdhci: use the host version value in sdhci_setup_cfgJaehoon Chung2016-10-10-1/+5
| | | | | | | | "host->version" isn't a SoC specific value. It doesn't need to get in each SoC drivers. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* mmc: sdhci: Add the programmable clock mode supportWenyou Yang2016-09-20-10/+40
| | | | | | Add the programmable clock mode for the clock generator. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* mmc: sdhci: drop CONFIG_ from CONFIG_SDHCI_CMD_MAX_TIMEOUTMasahiro Yamada2016-09-20-6/+3
| | | | | | | | | No need for per-SoC adjustment for this parameter. It should be determined by the slowest hardware. Currently, no board overrides this CONFIG, so 3.2 sec is large enough. (If not, we can make it even larger.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: sdhci: drop CONFIG_ from CONFIG_SDHCI_CMD_DEFAULT_TIMEMasahiro Yamada2016-09-20-2/+2
| | | | | | | | This CONFIG is not configurable since it is not guarded by #ifndef. Nobody has complained about that, so there is no need to keep it as a CONFIG option. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: sdhci: move SDMA capability check to sdhci_setup_cfg()Masahiro Yamada2016-09-20-11/+8
| | | | | | | | If CONFIG_BLK is enabled, add_sdhci() is never called. Move this quirk handling to sdhci_setup_cfg(), which is now the central place for hardware capability checks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: sdhci: move broken voltage quirk handling to sdhci_setup_cfg()Masahiro Yamada2016-09-20-3/+3
| | | | | | | | If CONFIG_BLK is enabled, add_sdhci() is never called. Move this quirk handling to sdhci_setup_cfg(), which is now the central place for hardware capability checks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: sdhci: move error message to more relevant placeMasahiro Yamada2016-09-20-6/+9
| | | | | | | | "Hardware doesn't specify base clock frequency" may not be only the error case of sdhci_setup_cfg(). It is better to print this where the corresponding error is triggered. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: sdhci: move sdhci_reset() call to sdhci_init()Masahiro Yamada2016-09-20-2/+2
| | | | | | | | | | | If CONFIG_BLK is enabled, add_sdhci() is never called. So, sdhci_reset() is not called, either. This is a problem for my board as it needs the reset to start from a sane state. Move the add_sdhci() call to sdhci_init(), which is visited by both of the with/without CONFIG_BLK cases. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: sdhci: fix the compiler warning when disable CONFIG_MMC_SDMAJaehoon Chung2016-08-05-1/+1
| | | | | | | When disabled CONFIG_MMC_SDMA, variable caps didn't use. This patch fixes the compiler error for -Wunused-but-set-variable Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: remove the unnecessary arguments for sdhci_setup_cfgJaehoon Chung2016-08-05-12/+14
| | | | | | | | | | | | | | Some arguments don't need to pass to sdhci_setup_cfg. Generic variable can be used in sdhci_setup_cfg, and some arguments are already included in sdhci_host struct. It's enough that just pass the board specific things to sdhci_setup_cfg(). After removing the unnecessary arguments, it's more simpler than before. It doesn't consider "Version" and "Capabilities" anymore in each SoC driver. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mmc: sdhci: remove the unused argument for sdhci_setup_cfgJaehoon Chung2016-08-05-2/+2
| | | | | | | | buswidth isn't used anywhere in sdhci_setup_cfg. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mmc: sdhci: revert "mmc: sdhci: Claer high speed if not supported"Jaehoon Chung2016-08-05-3/+0
| | | | | | | | | | | | | | | | This "commit 429790026021d522d51617217d4b86218cca5750" is wrong. SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit. For example, Exynos didn't have CTRL_HISPD. But Highspeed mode is supported. (This quirks doesn't mean that driver didn't support the Highseepd mode.) Note: If driver didn't support the Highspeed Mode, use or add the other quirks. After applied this patch, all Exynos SoCs are just running with 25MHz. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: use the generic error numberJaehoon Chung2016-08-05-4/+4
| | | | | | | | | Use the generic error number instead of specific error number. If use the generic error number, it can debug more easier. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* mmc: sdhci: set to INT_DATA_END when there are dataJaehoon Chung2016-08-05-1/+2
| | | | | | | | | | | | There is no data, it doesn't needs to wait for completing data transfer. (It seems that it can be removed.) Almost all timeout error is occured from stop command without data. After applied this patch, I hope that we don't need to increase timeout value anymore. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* mmc: sdhci: clean up timeout detectionMasahiro Yamada2016-08-05-9/+9
| | | | | | | | | | | | | The current timeout detection logic is not very nice; it calls get_timer(start) in the while() loop, and then calls it again after the loop to check if a timeout error happened. Because of the time difference between the two calls of get_timer(), the timeout detected after the loop may not be true. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: Disable internal clock enable bitSiva Durga Prasad Paladugu2016-07-22-1/+1
| | | | | | | | | | | Disable internal clock by clearing the internal clock enable bit. This bit needs to be cleared too when we stop the SDCLK for changing the frequency divisor. This bit should be set to zero when the device is not using the Host controller. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* dm: mmc: sdhci: Support CONFIG_BLK and CONFIG_DM_MMC_OPSSimon Glass2016-07-11-1/+39
| | | | | | | Add support for using driver model for block devices and MMC operations in this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: sdhci: Refactor configuration setup to support DMSimon Glass2016-07-11-48/+59
| | | | | | | Move the configuration setting into a separate function which can be used by the driver-model code. Signed-off-by: Simon Glass <sjg@chromium.org>
* mmc: increase MMC SDHCI read status timeoutSteve Rae2016-07-01-2/+3
| | | | | | | | | | | | | | | | | | | | | | Otherwise, ocassionally see errors like this: Flashing sparse image at offset 2078720 Flashing Sparse Image sdhci_send_command: Timeout for status update! mmc fail to send stop cmd write_sparse_image: Write failed, block #2181088 [0] This does not affect the actual writing speed, which is controlled by the default value: CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT It only increases the retries when reading: SDHCI_INT_STATUS to avoid the timeout error. Signed-off-by: Steve Rae <steve.rae@raedomain.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
* dm: mmc: Convert sdhci to support CONFIG_BLKSimon Glass2016-05-27-1/+1
| | | | | | Update sdhci.c so that it works with driver model enabled for block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: block: Rename device number member dev to devnumSimon Glass2016-03-14-1/+1
| | | | | | | | | This is a device number, and we want to use 'dev' to mean a driver model device. Rename the member. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* drivers: mmc: add driver for Microchip PIC32 SDHCI controller.Andrei Pistirica2016-02-01-0/+7
| | | | | | | | | | | This driver implements platform specific glue and fixups for PIC32 internal SDHCI controller. Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com> Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mmc: sdhci: Clear high speed if not supportedSiva Durga Prasad Paladugu2016-01-27-0/+4
| | | | | | | | | Clear high speed bit if it was not supported by the driver. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Emil Lenchak <emill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* mmc: sdhci: Fix the SD clock stop sequenceWenyou Yang2015-11-03-2/+18
| | | | | | | | | | | | According to the SDHC specification, stopping the SD Clock is by setting the SD Clock Enable bit in the Clock Control register at 0, instead of setting all bits at 0. Before stopping the SD clock, we need to make sure all SD transactions to complete, so add checking the CMD and DAT bits in the Presen State register, before stopping the SD clock. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* mmc: sdhci.c: Add config option to use a fixed buffer for transfersStefan Roese2015-07-10-0/+15
| | | | | | | | | | | | | | | | | | | | While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the following problem occured. The SPL runs in internal SRAM which is the L2 cache locked to memory. When the MMC buffers now are located on the stack (or bss), the SDIO controller (SDHCI) can't write into this L2 cache memory. This patch introduces a method to use a fixed buffer that will be used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER. This way, the board can use this buffer address located in SDRAM for all transfers. This solves this SPL problem on the A38x and should only be used in the SPL U-Boot version. Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* mmc: sdhci: Use timer based timeout detection in sdhci_send_command()Stefan Roese2015-07-10-5/+5
| | | | | | | | | | | | | The loop counter based timeout detection does not work on the Armada 38x based board (DB-88F6820-GP). At least with dcache enabled a timeout is detected. Without dcache enabled, the timeout does not occur. Increasing the loop counter solves this issue. But a better solution is to use a timer based timeout detection instead. This patch now implements this timer based detection. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* mmc: sdhci: add timeout setting for response busy commandKevin Liu2015-05-05-0/+2
| | | | | | | | | | Timeout interrupt also work for response busy command(R1b) like cmd38/cmd6. So need to set it accordingly. Current code only set timeout for data command. Signed-off-by: Kevin Liu <kliu5@marvell.com> Signed-off-by: Rob Herring <robh@kernel.org> Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
* sdhci: fix warnings on 64-bit buildsRob Herring2015-03-18-3/+3
| | | | | | | | Change addresses to unsigned long to be compatible with 64-bit builds. Regardless of fixing warnings, the device is still only 32-bit capable. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: sdhci: don't clobber adjacent registersMatt Reimer2015-03-18-1/+1
| | | | | | | | SDHCI_HOST_CONTROL is a byte-sized register, so don't write to it as if it were a long, as that would result in clobbering the three registers following. Signed-off-by: Matt Reimer <mreimer@sdgsystems.com>
* mmc: sdhci: fix bus width switching on Samsung SoCsMatt Reimer2015-02-23-1/+2
| | | | | | | | | | | | Fix bus width switching from 8-bit mode down to 4-bit or 1-bit modes on Samsung SoCs using SDHCI_QUIRK_USE_WIDE8. These SoCs report controller version 2.0 yet they support 8-bit bus widths. If 8-bit mode was previously enabled and then an operation like "mmc dev" caused a switch back down to 4-bit or 1-bit mode, WIDE8 was left set, causing failures. This problem was manifested by "mmc dev" timing out. Signed-off-by: Matt Reimer <mreimer@sdgsystems.com>
* sdhci: make local functions staticJeroen Hofstee2014-10-25-3/+3
| | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* mmc: Split mmc struct, rework mmc initialization (v2)Pantelis Antoniou2014-03-24-37/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way that struct mmc was implemented was a bit of a mess; configuration and internal state all jumbled up in a single structure. On top of that the way initialization is done with mmc_register leads to a lot of duplicated code in drivers. Typically the initialization got something like this in every driver. struct mmc *mmc = malloc(sizeof(struct mmc)); memset(mmc, 0, sizeof(struct mmc); /* fill in fields of mmc struct */ /* store private data pointer */ mmc_register(mmc); By using the new mmc_create call one just passes an mmc config struct and an optional private data pointer like this: struct mmc = mmc_create(&cfg, priv); All in tree drivers have been updated to the new form, and expect mmc_register to go away before long. Changes since v1: * Use calloc instead of manually calling memset. * Mark mmc_register as deprecated. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: Convert mmc struct's name array to a pointerPantelis Antoniou2014-03-24-1/+1
| | | | | | | Using an array is pointless; even more pointless (and scary) is using sprintf to fill it without a format string. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: Remove ops from struct mmc and put in mmc_opsPantelis Antoniou2014-03-24-5/+8
| | | | | | | | | | | | | | | | | Remove the in-structure ops and put them in mmc_ops with a constant pointer to it. This makes the mmc structure smaller as well as conserving code space (in theory). All in-tree drivers are converted as well; this is done in a single patch in order to not break git bisect. Changes since V1: Fix compilation b0rked issue on omap platforms where OMAP_GPIO was not set. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
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