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path: root/drivers/mmc/sdhci.c
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* mmc: Minor cleanup of sdhci.cDarwin Rambo2014-01-09-13/+19
| | | | | | | | Fixup prints to show where the print is done from, and a few minor formatting/grammar issues. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: sdhci: Avoid commands errors by simple timeout adaptation.Przemyslaw Marczak2013-10-31-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | Old command timeout value was too small and it caused I/O errors which led to uncompleted read/write/erase operations and filesystem errors. Timeout adaptation fixes this issue. Changes in sdhci_send_command() function: - change timeout variable to static - increase default command timeout to 100 ms - add definition of max command timeout value, which can be redefined in each board config file - wait for card ready state for max defined time if it doesn't exceed defined maximum or return COMM_ERR Once successfully increased timeout value will be used in next function call. This fix was tested on Goni, Trats, Trats2 boards by testing UMS on MMC storage. Changes v2: - move global variable cmd_timeout into function sdhci_send_command() - change condition "==" to ">=" when comparing time with timeout - print information about timeout increasing and card busy timeout Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
* Fix wrong sdhci host control register read and writeJuhyun \(Justin\) Oh2013-09-20-3/+2
| | | | | | | | | | | | | | | | The patch fixes the improper read and write of sdhci host control register for sdma transfer. The problem comes when reading and writing 1 byte long host control register with the sdhci_readl() and sdhci_writel(). The misuse of these functions overwrite the value of the next registers which are in 4 bytes boundary. This patch replaces four byte register read/write functions with one byte read/write ones. Beside, it eliminates unnecessary bit operation. i.e. or-ing zero against a variable. Signed-off-by: Juhyun (Justin) Oh <Juhyun_Oh@sigmadesigns.com>
* mmc: sdhci: use the SDHCI_QUIRK_USE_WIDE8 for samsung SoCJaehoon Chung2013-09-17-6/+7
| | | | | | | | | Samsung SoC is supported the WIDE8, even if Controller version is v2.0. So add the SDHCI_QUIRK_USE_WIDE8 for Samsung-SoC. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* mmc: sdhci: Enable 8-bit bus width only for 3.0 spec onwardsJagannadha Sutradharudu Teki2013-06-13-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | CAP register don't have any information for 8-bit buswidth support on 2.0 sdhci spec, only from 3.0 onwards bit[18] got this information. Due to this misassignment in sdhci, mmc is setting 8-bit buswidth using mmc_set_bus_width even if controller doesn't support. Below change has code information. "mmc: Properly determine maximum supported bus width" (sha1: 7798f6dbd5e1a3030ed81a81da5dfb57c3307cac) Bug log: <mmc plus and emmc cards) ------- zynq-uboot> mmcinfo Error detected in status(0x208100)! Device: zynq_sdhci Manufacturer ID: fe ..... So enable 8-bit support only for 3.0 spec using CAP and for below 3.0 assign mmc->host_caps = MMC_MODE_8BIT on respective platform driver if host have a support. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-26-3/+5
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| * mmc:sdhci:fix: Change default interrupts enabled at SDHCI initializationŁukasz Majewski2013-03-12-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes sdhci_init()'s behavior to NOT enable all interrupt sources by default. Moreover interrupt signaling has been disabled. This patch do not enable interrupts which aren't served in u-boot (they are defined at sdhci.h but NOT used elsewhere): - SDHCI_INT_CARD_INSERT, SDHCI_INT_CARD_REMOVE, SDHCI_BUS_POWER, SDHCI_INT_CARD_REMOVE, SDHCI_INT_CARD_INT Special care shall be put on SDHCI_INT_CARD_INT, which indicates interrupt generated by SD card. According to "SD Host Controller Simplified Spec. ver 3.00" when bit 8 (Card Interrupt Status Enable) at "Normal Interrupt Status Enable Register" (offset 0x34) is set, the card interrupt detection is started. Then eMMC card may cause the SD controller to set this bit and then this interrupt is passed to booted OS and might cause kernel crash. To sum up: - Only enable interrupts, which are served at u-boot - This cleanup as a side effect fixes SDHCI's CARD INTERRUPT problem at Linux kernel (versions 3.6+, sdhci controller) - Keep masked bits at "Normal Interrupt Signal Enable Register" (0x38h) Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Andy Fleming <afleming@freescale.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | mmc: add support for write protectionNikita Kiryanov2013-03-08-0/+1
|/ | | | | | | Add generic mmc write protection functionality. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* mmc: add no simultaenous power and vddMela Custodio2012-11-27-0/+3
| | | | | | | | | | | | | | | | | | Bring in the code from Linux kernel. Added to Linux kernel by: commit e08c1694d9e2138204f2b79b73f0f159074ce2f5 Author: Andres Salomon <dilinger@queued.net> Date: Fri Jul 4 10:00:03 2008 -0700 Some HW balks when writing both voltage setting and power up at the same time to SDHCI_POWER_CONTROL register. Signed-off-by: Rommel G Custodio <sessyargc@gmail.com> CC: Andy Fleming <afleming@freescale.com> v2: fix attribution and SOB Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: sdhci: Add a quirk to add delay during completion of sdhci_send_cmdTushar Behera2012-10-22-0/+3
| | | | | | | | | | | | | | | | | MMC host controller requires a delay between every sdhci_send_cmd() execution. In s5p_mmc driver (s5p_sdhci replaces this driver), a delay of 1000us was provided after every mmc_send_cmd() call. Adding a quirk in current sdhci driver to replicate the behaviour. Without this delay, MMC initialization on Origen board fails with following error messages. Timeout for status update! mmc fail to send stop cmd Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: sdhci: add the DMA select for SDMAJaehoon Chung2012-10-22-0/+7
| | | | | | | | | | In host-control register, DMA select bit field is present. BUt in sdhci.c, didn't select for DMA. if set CONFIG_MMC_SDMA, we need to set SDMA-select bit. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: sdhci: increase the timeout value for data transferJaehoon Chung2012-10-22-1/+1
| | | | | | | | | | | | Timeout value is tunable. When run read/write operation, sometime returned the timeout error. Because the timeout value is too short. So increased the enough timeout value. (This timeout value is used to prevent the infinite loop.) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: s5p_sdhci: add the set_mmc_clk for cmu controlJaehoon Chung2012-09-05-0/+3
| | | | | | | | Samsung SoC use the cmu control to set clock. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: Add a SDHCI quirk for boards that have no CDJoe Hershberger2012-09-05-2/+15
| | | | | | | | Some boards have no Card Detect wired. In that case, set the CD test bits in the standard interface. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: Fix version check for clock API in sdhci driverJoe Hershberger2012-09-05-5/+5
| | | | | | | | | | When setting up the clocks in the sdhci driver, the "spec version" must be masked off. Otherwise any time the vendor version is not 0, the check will allways assume the interface is version 3. This breaks when the interface is actually version 1 or 2. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: add the quirk to use the sdhci for samsung-socJaehoon Chung2012-05-08-0/+12
| | | | | | | | | | To support the Samsung-SoC, added the basically functions. Samsung-SoC didn't used the SDHCI_CTRL_HISPD. And added set_control_reg callback for s3c64xx. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Lei Wen<leiwen@marvell.com>
* mmc: sdhci: add the quirk for broken r1b responseJaehoon Chung2012-05-08-0/+12
| | | | | | | | | | | | | | When response type is R1b, mask value is added the SDHCI_INT_DAT_END. but in while(), didn't check that flag. So sdhci controller didn't work fine. CMD6 didn't always complete. So add the quirks for broken r1b response and add the timeout value to prevent the infinite loop. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Lei Wen<leiwen@marvell.com>
* mmc: Implement card detection.Thierry Reding2012-01-08-0/+1
| | | | | | | | | | | Check for card detect each time an MMC/SD device is initialized. If card detection is not implemented, this code behaves as before and continues assuming a card is present. If no card is detected, has_init is reset for the MMC/SD device (to force initialization next time) and an error is returned. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Jason Liu <jason.hui@linaro.org>
* mmc: sdhci: fix sdma bug for large file transferLei Wen2011-11-03-1/+1
| | | | | | | | | SDHCI spec need to reset the sdma base address while the software try to accorss the 512k bytes address boundary. When meet such accross behavior, sdhci controller would generate a interrupt automatically, and software need handle this. Signed-off-by: Lei Wen <leiwen@marvell.com>
* mmc: sdhci: add timeout for data transferLei Wen2011-11-03-1/+8
| | | | Signed-off-by: Lei Wen <leiwen@marvell.com>
* mmc: sdhci: add mmc structure for hostLei Wen2011-11-03-0/+1
| | | | | | | So that sdhci host would tell in the driver that the mmc current attributes. Signed-off-by: Lei Wen <leiwen@marvell.com>
* mmc: sdhci: fix cache flushLei Wen2011-11-03-1/+1
| | | | | | Only flush the memory range needed. Signed-off-by: Lei Wen <leiwen@marvell.com>
* MMC: add sdhci generic frameworkLei Wen2011-07-15-0/+433
Nowdays, there are plenty of mmc driver in uboot adopt the sd standard host design, aka as sdhci. It is better to centralize the common logic together to better maintenance. Signed-off-by: Lei Wen <leiwen@marvell.com> Acked-by: Andy Fleming <afleming@freescale.com>
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