summaryrefslogtreecommitdiff
path: root/drivers/mmc/fsl_esdhc.c
Commit message (Collapse)AuthorAgeLines
* dm: core: Replace of_offset with accessorSimon Glass2017-02-08-1/+1
| | | | | | | | | At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-01-19-9/+23
|\
| * mmc: fsl_esdhc: move 'status' property fixup into a weak functionYangbo Lu2017-01-18-7/+14
| | | | | | | | | | | | | | | | Move fdt fixup of 'status' property into a weak function. This allows board to define 'status' fdt fixup by themselves. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * mmc: fsl_esdhc: add 'fsl, esdhc' into of_match tableYangbo Lu2017-01-18-0/+1
| | | | | | | | | | | | | | | | This patch is to add 'fsl,esdhc' into of_match table to support driver model for QorIQ eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * mmc: fsl_esdhc: make GPIO support optionalYangbo Lu2017-01-18-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | There would be compiling error as below when enable driver model for esdhc. undefined reference to `dm_gpio_get_value' undefined reference to `gpio_request_by_name_nodev' This patch is to make GPIO support optional with CONFIG_DM_GPIO. Because all boards of QorIQ platform don't need it and they just check register for CD/WP status, only some boards of i.MX platform require this. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | mmc: change the set_ios return type from void to intJaehoon Chung2017-01-11-1/+2
|/ | | | | | To maintain consistency, set_ios type of legacy mmc_ops changed to int. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* dm: mmc: intialize dev when probePeng Fan2016-10-04-0/+1
| | | | | | | | | | | Need to initialize mmc->dev when probe, or will met "dev_get_uclass_priv: null device", when `mmc dev 1`. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mmc: use the generic error numberJaehoon Chung2016-08-05-6/+7
| | | | | | | | | Use the generic error number instead of specific error number. If use the generic error number, it can debug more easier. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* mmc: fsl_esdhc: remove the duplicated header fileJaehoon Chung2016-08-05-1/+0
| | | | | | | "mmc.h" is already included. It's duplicated. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mmc: fsl: introduce wp_enablePeng Fan2016-06-28-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | Introudce wp_enable. To check WPSPL, wp_enable needs to be set to 1 in board code. Take i.MX6UL for example, for some boards, they do not use WP singal, so they does not configure USDHC1_WP_SELECT_INPUT, and its default value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and SION bit set. So USDHC controller can always get wp signal and WPSPL shows write protect and blocks driver continuing. This is not what we want to see, so add wp_enable, and if set to 0, just omit the WPSPL checking and this does not effect normal working of usdhc controller. If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl_esdhc: Update clock enable bits for USDHCYe Li2016-06-28-2/+7
| | | | | | | | | | | | | | | | | | | | | | | The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN, HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec register. The driver uses RSTA to replace the clock gate off operation. But this is not a good solution because: 1. when using RSTA, we should wait this bit to clear by itself. This is not implemeneted in the code. 2. After RSTA is set, it is recommended that the Host Driver reset the external card and reinitialize it. So in this patch, we change to use the vendorspec registers for these bits operation. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* mmc: fsl: reset to normal boot mode when eMMC fast bootPeng Fan2016-06-28-9/+29
| | | | | | | | | | | | | | | | | | | | | When booting in eMMC fast boot, MMC host does not exit from boot mode after bootrom loading image. So the first command 'CMD0' sent in uboot will pull down the CMD line to low and cause errors. This patch cleans the MMC boot register in "mmc_init" to put the MMC host back to normal mode. Also clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: s32v234: Introduce basic support for s32v234evbEddy Petrișor2016-06-13-4/+4
| | | | | | | | | | | | | | | | Add initial support for NXP's S32V234 SoC and S32V234EVB board. The S32V230 family is designed to support computation-intensive applications for image processing. The S32V234, as part of the S32V230 family, is a high-performance automotive processor designed to support safe computation-intensive applications in the area of vision and sensor fusion. Code originally writen by: Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com> Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com> Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
* mmc: fsl_esdhc: fix check_and_invalidate_dcache_range functionYangbo Lu2016-06-03-5/+4
| | | | | | | | | In function check_and_invalidate_dcache_range(), there are incorrect start address and end address of the dcache range calculated for Layerscape platforms. This patch is to fix this issue. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl: esdhc: support driver modelPeng Fan2016-04-06-40/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support Driver Model for fsl esdhc driver. 1. Introduce a new structure struct fsl_esdhc_priv 2. Refactor fsl_esdhc_initialize which is originally used by board code. - Introduce fsl_esdhc_init to be common usage for DM and non-DM - Introduce fsl_esdhc_cfg_to_priv to build the bridge for non-DM part. - The original API for board code is still there, but we use 'fsl_esdhc_cfg_to_priv' and 'fsl_esdhc_init' to serve it. 3. All the functions are changed to use 'struct fsl_esdhc_priv', except fsl_esdhc_initialize. 4. Since clk driver is not implemented, use mxc_get_clock to geth the clk and fill 'priv->sdhc_clk'. Has been tested on i.MX6UL 14X14 EVK board: " =>dm tree .... simple_bus [ + ] | `-- aips-bus@02100000 mmc [ + ] | |-- usdhc@02190000 mmc [ + ] | |-- usdhc@02194000 .... => mmc list FSL_SDHC: 0 (SD) FSL_SDHC: 1 (SD) " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Yangbo Lu <yangbo.lu@nxp.com> Cc: Hector Palacios <hector.palacios@digi.com> Cc: Eric Nelson <eric@nelint.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Simon Glass <sjg@chromium.org> Tested-By: Eric Nelson <eric@nelint.com> Reviewed-by: York Sun <york.sun@nxp.com>
* mmc: fsl_esdhc: set Abort command type for CMD12Yangbo Lu2016-01-27-4/+1
| | | | | | | | | According to SD spec, CMD12, CMD52 for writing I/O abort in CCCR need to be set an Abort command type when they are sent. So, we remove all chip-specific #ifdefs and make it available for all platforms. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* mmc: fsl_esdhc: increase data transaction timeout to 500msYangbo Lu2016-01-27-1/+8
| | | | | | | | | | The MMC spec says "It is strongly recommended for hosts to implement more than 500ms timeout value even if the card indicates the 250ms maximum busy length." Even the previous value of 300ms is known to be insufficient for some cards. So, increase the timeout to 500ms. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARM: imx: fsl_esdhc: fix usage of low 4 bits of sysctl registerEric Nelson2016-01-03-2/+13
| | | | | | | | | | | | | | | | | | | | | | The low four bits of the SYSCTL register are reserved on the USDHC controller on i.MX6 and i.MX7 processors, but are used for clocking operations on earlier models. Guard against their usage by hiding the bit mask macros on those processors. These bits are used to prevent glitches when changing clocks on i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7. >From the i.MX6DQ RM: To prevent possible glitch on the card clock, clear the FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS or DVS in System Control Register) or setting RSTA bit. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Hector Palacios <hector.palacios@digi.com>
* mmc: fsl_esdhc: enable EVDD automatic control for SD/MMC Legacy Adapter CardYangbo Lu2015-11-02-0/+3
| | | | | | | | | When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card), enable EVDD automatic control via SDHC_VS. This could support SD card IO voltage switching for UHS-1 speed mode. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5 Adapter CardYangbo Lu2015-11-02-0/+3
| | | | | | | | If adapter card type identification is supported for platform, we would enable dat[4:7] for eMMC4.5 Adapter Card. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Powerpc: eSDHC: expand a fix to T4160Shaohui Xie2015-11-02-1/+2
| | | | | | | | commit b8e5b07225 "Powerpc: eSDHC: Fix mmc read write err in uboot of T4240QDS board", T4160 also needs this fix. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardbYangbo Lu2015-10-29-6/+6
| | | | | | | | This patch adds esdhc support for ls1043ardb. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl_esdhc.c: Always make check_and_invalidate_dcache_range availableTom Rini2015-08-02-2/+0
| | | | | | | This function is called from esdhc_send_cmd so we need it available to everyone. Signed-off-by: Tom Rini <trini@konsulko.com>
* mmc:fsl_esdhc invalidate dcache before readPeng Fan2015-07-26-0/+8
| | | | | | | | | | | | | | | | | | | | | DCIMVAC is upgraded to DCCIMVAC for the individual processor (Cortex-A7) that the DCIMVAC is executed on. We should follow the linux dma follow. Before DMA read, first invalidate dcache then after DMA read, invalidate dcache again. With the DMA direction DMA_FROM_DEVICE, the dcache need be invalidated again after the DMA completion. The reason is that we need explicity make sure the dcache been invalidated thus to get the DMA'ed memory correctly from the physical memory. Any cache-line fill during the DMA operations such as the pre-fetching can cause the DMA coherency issue, thus CPU get the stale data. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* Merge git://git.denx.de/u-boot-mpc85xxTom Rini2015-05-05-1/+78
|\
| * mmc: fsl_esdhc: Add peripheral clock supportYangbo Lu2015-05-04-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | The SD clock could be generated by platform clock or peripheral clock for some platforms. This patch adds peripheral clock support for T1024/T1040/T2080. To enable it, define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mmc: fsl_esdhc: Add adapter card type identification supportYangbo Lu2015-05-04-1/+37
| | | | | | | | | | | | | | | | | | | | | | | | Add adapter card type identification support by reading FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function, define CONFIG_FSL_ESDHC_ADAPTER_IDENT. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> [York Sun: resolve conflicts in README.fsl-esdhc] Reviewed-by: York Sun <yorksun@freescale.com>
* | mmc: fsl_esdhc: update eMMC44 adapter card erase timeoutYangbo Lu2015-05-05-2/+2
| | | | | | | | | | | | | | | | | | Freescale eMMC44 adapter card uses Micron N2M400FDB311A3CF eMMC memory. According to the silicon datasheet, secure erase timeout is 600ms. So increase erase timeout value from 250ms to 600ms. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com>
* | mmc: remove the MMC_MODE_HC flagRob Herring2015-05-05-1/+1
|/ | | | | | | | | | | | | High capacity support is not a host capability, but a device capability that is queried via the OCR. The flag in the operating conditions request argument can just be set unconditionally. This matches the Linux implementation. [panto] Hand merged and renumbering MMC_MODE_DDR_52MHz. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
* ls2085a: esdhc: Add esdhc support for ls2085aYangbo Lu2015-04-23-2/+34
| | | | | | | This patch adds esdhc support for ls2085a. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* mmc: fsl_esdhc fix register offsetPeng Fan2015-03-17-1/+1
| | | | | | | | | | Commit f022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 introduces error register offset. Change the "char reserved3[59]" to "char reserved3[56]". Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-03-02-2/+6
|\
| * mmc: fsl_esdhc: Add support for DDR modeVolodymyr Riazantsev2015-02-24-2/+6
| | | | | | | | | | | | | | | | Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only. Signed-off-by: Volodymyr Riazantsev <volodymyr.riazantsev@globallogic.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | mmc: fsl_esdhc: Add support to force VSELECT setOtavio Salvador2015-02-23-0/+4
| | | | | | | | | | | | | | | | | | Some boards cannot do voltage negotiation but need to set the VSELECT bit forcely to ensure it to work at 1.8V. This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | mmc: fsl_esdhc: Add CMD11 support to switch to 1.8VOtavio Salvador2015-02-23-7/+22
|/ | | | | | | This adds support to switch to 1.8V in case CMD11 succeeds. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Marek Vasut <marex@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-11-26-1/+1
|\ | | | | | | | | | | | | Conflicts: drivers/mmc/fsl_esdhc.c Signed-off-by: Tom Rini <trini@ti.com>
| * mmc: fsl_esdhc: fix f_max retrieval during initMarkus Niebel2014-11-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | for multi instance API we use struct fsl_esdhc_cfg to pass the clock rate. Do not set f_max from global data, since this is wrong for multi instance case. Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: Stefano Babic <sbabic@denx.de> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-24-0/+8
|\ \
| * | mmc: fsl_esdhc: Update esdhc driver for iMX6SXYe.Li2014-11-20-0/+8
| |/ | | | | | | | | | | | | | | The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0 on iMX6SX. So the fsl_esdhc driver must update to set the register, otherwise no state can be detected. Signed-off-by: Ye.Li <B37916@freescale.com>
* | linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2014-11-23-1/+1
|/ | | | | | | | | | | | | | | | | | | | U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
* cosmetic: replace MIN, MAX with min, maxMasahiro Yamada2014-09-24-1/+1
| | | | | | | The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ls102xa: esdhc: Add esdhc support for LS102xAWang Huan2014-09-08-2/+2
| | | | | | | | | | | For LS1, esdhc is big-endian IP. Accessing the registers should be in big-endian mode. So we use esdhc_read32() to read Host controller capabilities register for LS1. For LS1, when using CMD12, cmdtype need to be set to ABORT, otherwise, next read command will hang. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* esdhc/usdhc: Fix warning when CONFIG_SYS_FSL_ESDHC_USE_PIO is not setTom Rini2014-05-23-0/+3
| | | | | | | | In 7168977 we made calls to check_and_invalidate_dcache_range() conditional on !CONFIG_SYS_FSL_ESDHC_USE_PIO. Only define this function in this case as well. Signed-off-by: Tom Rini <trini@ti.com>
* esdhc/usdhc: Fix PIO mode bug in fsl_esdhc driverYe.Li2014-05-22-14/+9
| | | | | | | | | | | | | | | When configure the fsl_esdhc driver to PIO mode by defining "CONFIG_SYS_FSL_ESDHC_USE_PIO", the SD/MMC read and write will fail. Two bugs in the driver to cause the issue: 1. The read buffer was invalidated after reading from DATAPORT register, which should be only applied to DMA mode. The valid data in cache was overwritten by physical memory. 2. The watermarks are not set in PIO mode, will cause according state not be set. Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* powerpc/85xx: Add T4240RDB board supportChunhe Lan2014-05-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]
* mmc:eSDHC: Workaround for data timeout issue on Txxx SoCHaijun.Zhang2014-04-02-0/+3
| | | | | | | | | | | | | | 1. The Data timeout counter value in eSDHC_SYSCTL register is not working as it should be, so add quirks to enable this workaround to fix it to the max value 0xE. 2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround. * Update of patch for change mmc interface by Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: fsl_esdhc: add controller reset in case of data related errors tooAndrew Gabbasov2014-04-02-27/+36
| | | | | | | | The controller reset is performed now if command error occurs. This commit adds the reset for the case of data related errors too. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: fsl_esdhc: fix calculation of timeout for data transactionsAndrew Gabbasov2014-04-02-6/+6
| | | | | | | | | | | | | | | Calculation of the timeout value should be based on actual clock value, written to controller registers. Since mmc->tran_speed is either the maximum allowed speed, or the preliminary value, that is be not yet set to registers, the actual timeout, taken by the controller, based on its clock settings, may be much longer than expected, based on mmc->tran_speed value. In particular it happens at early initialization stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while actual clock setting, configured in the controller, is 400kHz. It's more correct to use mmc->clock value for timeout calculation instead. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: Split mmc struct, rework mmc initialization (v2)Pantelis Antoniou2014-03-24-28/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way that struct mmc was implemented was a bit of a mess; configuration and internal state all jumbled up in a single structure. On top of that the way initialization is done with mmc_register leads to a lot of duplicated code in drivers. Typically the initialization got something like this in every driver. struct mmc *mmc = malloc(sizeof(struct mmc)); memset(mmc, 0, sizeof(struct mmc); /* fill in fields of mmc struct */ /* store private data pointer */ mmc_register(mmc); By using the new mmc_create call one just passes an mmc config struct and an optional private data pointer like this: struct mmc = mmc_create(&cfg, priv); All in tree drivers have been updated to the new form, and expect mmc_register to go away before long. Changes since v1: * Use calloc instead of manually calling memset. * Mark mmc_register as deprecated. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: Convert mmc struct's name array to a pointerPantelis Antoniou2014-03-24-1/+1
| | | | | | | Using an array is pointless; even more pointless (and scary) is using sprintf to fill it without a format string. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
generated by cgit v1.1 at 2024-12-27 13:52:32 +0000