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path: root/drivers/mmc/fsl_esdhc.c
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* ls102xa: esdhc: Add esdhc support for LS102xAWang Huan2014-09-08-2/+2
| | | | | | | | | | | For LS1, esdhc is big-endian IP. Accessing the registers should be in big-endian mode. So we use esdhc_read32() to read Host controller capabilities register for LS1. For LS1, when using CMD12, cmdtype need to be set to ABORT, otherwise, next read command will hang. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* esdhc/usdhc: Fix warning when CONFIG_SYS_FSL_ESDHC_USE_PIO is not setTom Rini2014-05-23-0/+3
| | | | | | | | In 7168977 we made calls to check_and_invalidate_dcache_range() conditional on !CONFIG_SYS_FSL_ESDHC_USE_PIO. Only define this function in this case as well. Signed-off-by: Tom Rini <trini@ti.com>
* esdhc/usdhc: Fix PIO mode bug in fsl_esdhc driverYe.Li2014-05-22-14/+9
| | | | | | | | | | | | | | | When configure the fsl_esdhc driver to PIO mode by defining "CONFIG_SYS_FSL_ESDHC_USE_PIO", the SD/MMC read and write will fail. Two bugs in the driver to cause the issue: 1. The read buffer was invalidated after reading from DATAPORT register, which should be only applied to DMA mode. The valid data in cache was overwritten by physical memory. 2. The watermarks are not set in PIO mode, will cause according state not be set. Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* powerpc/85xx: Add T4240RDB board supportChunhe Lan2014-05-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]
* mmc:eSDHC: Workaround for data timeout issue on Txxx SoCHaijun.Zhang2014-04-02-0/+3
| | | | | | | | | | | | | | 1. The Data timeout counter value in eSDHC_SYSCTL register is not working as it should be, so add quirks to enable this workaround to fix it to the max value 0xE. 2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround. * Update of patch for change mmc interface by Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: fsl_esdhc: add controller reset in case of data related errors tooAndrew Gabbasov2014-04-02-27/+36
| | | | | | | | The controller reset is performed now if command error occurs. This commit adds the reset for the case of data related errors too. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: fsl_esdhc: fix calculation of timeout for data transactionsAndrew Gabbasov2014-04-02-6/+6
| | | | | | | | | | | | | | | Calculation of the timeout value should be based on actual clock value, written to controller registers. Since mmc->tran_speed is either the maximum allowed speed, or the preliminary value, that is be not yet set to registers, the actual timeout, taken by the controller, based on its clock settings, may be much longer than expected, based on mmc->tran_speed value. In particular it happens at early initialization stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while actual clock setting, configured in the controller, is 400kHz. It's more correct to use mmc->clock value for timeout calculation instead. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: Split mmc struct, rework mmc initialization (v2)Pantelis Antoniou2014-03-24-28/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way that struct mmc was implemented was a bit of a mess; configuration and internal state all jumbled up in a single structure. On top of that the way initialization is done with mmc_register leads to a lot of duplicated code in drivers. Typically the initialization got something like this in every driver. struct mmc *mmc = malloc(sizeof(struct mmc)); memset(mmc, 0, sizeof(struct mmc); /* fill in fields of mmc struct */ /* store private data pointer */ mmc_register(mmc); By using the new mmc_create call one just passes an mmc config struct and an optional private data pointer like this: struct mmc = mmc_create(&cfg, priv); All in tree drivers have been updated to the new form, and expect mmc_register to go away before long. Changes since v1: * Use calloc instead of manually calling memset. * Mark mmc_register as deprecated. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: Convert mmc struct's name array to a pointerPantelis Antoniou2014-03-24-1/+1
| | | | | | | Using an array is pointless; even more pointless (and scary) is using sprintf to fill it without a format string. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: Remove ops from struct mmc and put in mmc_opsPantelis Antoniou2014-03-24-6/+8
| | | | | | | | | | | | | | | | | Remove the in-structure ops and put them in mmc_ops with a constant pointer to it. This makes the mmc structure smaller as well as conserving code space (in theory). All in-tree drivers are converted as well; this is done in a single patch in order to not break git bisect. Changes since V1: Fix compilation b0rked issue on omap platforms where OMAP_GPIO was not set. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* esdhc: Detecting 8 bit width before mmc initializationHaijun.Zhang2014-01-22-0/+5
| | | | | | | | | | The upper 4 data signals of esdhc are shared with spi flash. So detect if the upper 4 pins are assigned to esdhc before enable sdhc 8 bit width. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
* esdhc: Workaround for card can't be detected on T4240QDSHaijun.Zhang2014-01-22-0/+4
| | | | | | | | | | | | | | | Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board. 1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there. 2. Card detecting pin is functional for SDHC card in Rev2.0. This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/esdhc: Add 3.3v voltage support in esdhc capacity registerHaijun.Zhang2013-10-31-0/+6
| | | | | | | | | | T4240QDS eSDHC host capabilities reigster should have VS33 bit define. Add quirk CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 to deal with capacity missing Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* esdhc: memset mmc struct before putting into useHaijun.Zhang2013-10-31-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct mmc should be clear to all '0' after malloc to avoid unexpect variable value. Like mmc->has_init = xxx. In this case mmcinfo will believe the card had been initialized before and skip the initialization. Test on P5040 and T4240, Error Log: => mmcinfo Device: FSL_SDHC Manufacturer ID: 0 OEM: 0 Name: Tran Speed: 0 Rd Block Len: 0 MMC version 0.0 High Capacity: No Capacity: 0 Bytes Bus Width: 0-bit => Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Signed-off-by: Xie Shaohui-B21989 <B21989@freescale.com> Tested-by: Ryan Barnett <rjbarnet@rockwellcollins.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* Powerpc/esdhc: Add simple description of esdhc registerHaijun.Zhang2013-10-31-37/+37
| | | | | | | Add some descriptions for esdhc register for easily using. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* powerpc/esdhc: Map register for eSDHC Host Controller V3.0Haijun.Zhang2013-10-31-2/+14
| | | | | | | | | eSDHC host controller has new register to support SD Spec 3.0. And the according host controller version was Freescale eSDHC Version 3.0. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: fsl_esdhc: Check the result from malloc()Fabio Estevam2013-09-20-0/+2
| | | | | | malloc can fail, so we should better check its return value before using it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* fsl_esdhc: Touch only relevant sys ctrl bitsDirk Behme2013-07-16-3/+3
| | | | | | | | | | | | | Dealing with the sys ctrl register should touch only the relevant bits and not accidently the whole register. On i.MX6, the sys control register contains bits which shouldn't be reset to 0, e.g. SYS_CTRL[3-0] and IPP_RST_N (SYS_CTRL[23]). Do this by read/modify/write instead of just a 32bit write. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Powerpc: eSDHC: Fix mmc read write err in uboot of T4240QDS boardHaijun.Zhang2013-07-16-1/+1
| | | | | | | | | Fill the right command type when using CMD12 to stop data transfer. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> CC: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> CC: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fsl_esdhc: Do not clear interrupt status bits until data processedAndrew Gabbasov2013-06-13-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After waiting for the command completion event, the interrupt status bits, that occured to be set by that time, are cleared by writing them back. It is supposed, that it should be command related bits (command complete and may be command errors). However, in some cases the DMA already completes by that time before the full transaction completes. The corresponding DINT bit gets set and then cleared before even entering the loop, waiting for data part completion. That waiting loop never gets this bit set, causing the operation to hang. This is reported to happen, for example, for write operation of 1 sector to upper area (block #7400000) of SanDisk Ultra II 8GB card. The solution could be to explicitly clear only command related interrupt status bits. However, since subsequent processing does not rely on any command bits state, it could be easier just to remove clearing of any bits at that point, leaving them all until all data processing completes. After that the whole register will be cleared at once. Also, on occasion, interrupts masking moved to before writing the command, just for the case there should be no chance of interrupt between the first command and interrupts masking. Reported-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: fsl_esdhc: Fix hang after 'save' commandFabio Estevam2013-06-13-1/+1
| | | | | | | | | | | | Since commit 48e0b2bd (powerpc/esdhc: Correct judgement for DATA PIO mode) we see mx6 systems to hang after doing a 'save' command. Revert this commit since the original 'ifdef' logic from 7b43db92 (drivers/mmc/fsl_esdhc.c: fix compiler warnings) was the correct one. Reported-by: Tapani Utriainen <tapani@technexion.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/esdhc: Correct judgement for DATA PIO modeHaijun.Zhang2013-05-15-1/+1
| | | | | | | | | | | | The logic for the whether to configure for polling or DMA was mistakenly reversed in this patch: Commit 7b43db92110ec2f15c5f7187a165f2928464966b drivers/mmc/fsl_esdhc.c: fix compiler warnings Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> CC: Sun Yusong-R58495 <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: fsl_esdhc: Use calloc()Fabio Estevam2013-05-06-2/+1
| | | | | | | A malloc() followed by memset() can be simply replaced by calloc(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fsl_esdhc: Fix DMA transfer completion waiting loopAndrew Gabbasov2013-04-14-2/+1
| | | | | | | | | | | Rework the waiting for transfer completion loop condition to continue waiting until both Transfer Complete and DMA End interrupts occur. Checking of DLA bit in Present State register looks not needed in addition to interrupts status checking, so it can be removed from the condition. Also, DMA Error condition is added to the list of data errors, checked in the loop. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
* fsl_esdhc: flush cache after IO completionEric Nelson2013-04-14-3/+2
| | | | | | | | | The cache should invalidate the read buffer for the SD card interface after the transfer complete, not command-complete. Tested-by: Andrew Gabbasov <Andrew_Gabbasov@mentor.com> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a boardAbbas Raza2013-04-03-0/+7
| | | | | | | | | | | | | | | | | | Maximum bus width supported by some i.MX6 boards is not 8bit like others. In case where both host controller and card support 8bit transfers, they agree to communicate on 8bit interface while some boards support only 4bit interface. Due to this reason the mmc 8bit default mode fails on these boards. To rectify this, define maximum bus width supported by these boards (4bit). If max_bus_width is not defined, it is 0 by default and 8bit width support will be enabled in host capabilities otherwise host capabilities are modified accordingly. It is tested with a MMCplus card. Signed-off-by: Abbas Raza <Abbas_Raza@mentor.com> cc: stefano Babic <sbabic@denx.de> cc: Andy Fleming <afleming@gmail.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
* mmc: add support for write protectionNikita Kiryanov2013-03-08-0/+1
| | | | | | | Add generic mmc write protection functionality. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* ppc: arm: Move sdhc_clk into arch_global_dataSimon Glass2013-02-04-3/+3
| | | | | | | This is used by both powerpc and arm, but I think it still qualifies as architecture-specific. Signed-off-by: Simon Glass <sjg@chromium.org>
* fsl_esdhc: add MMC_MODE_HC host_capsShawn Guo2013-01-05-1/+1
| | | | | | | | All esdhc variants we know should support high capacity MMC cards, so let's add MMC_MODE_HC host_caps unconditionally to support those MMC cards (capacity > 2 GB). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-11-05-1/+2
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| * mxc: Fix SDHC multi-instance clockBenoît Thébaudeau2012-10-16-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On mxc, each SDHC instance has a dedicated clock, so gd->sdhc_clk is not suitable for the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). This patch fixes this issue by adding a configuration field for the SDHC input clock frequency. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jason Liu <r64343@freescale.com> Cc: Matt Sealey <matt@genesi-usa.com> Cc: Andy Fleming <afleming@gmail.com>
* | drivers/mmc/fsl_esdhc.c: sparse fixesKim Phillips2012-11-04-2/+2
|/ | | | | | | fsl_esdhc.c:71:6: warning: symbol 'esdhc_xfertyp' was not declared. Should it be static? fsl_esdhc.c:413:6: warning: symbol 'set_sysctl' was not declared. Should it be st Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* fsl_esdhc: Remove cache snooping for i.MXBenoît Thébaudeau2012-09-01-2/+3
| | | | | | | | | | | | | | | The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so disable it globally for this architecture. This avoids setting no_snoop for all i.MX boards, and it prevents setting a reserved bit of a reserved register if fsl_esdhc_mmc_init() is used on i.MX, like in arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init(). Since no_snoop was only used on i.MX, get rid of it BTW. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com>
* FSL/eSDHC: enable the clock to detect the SD cardJerry Huang2012-07-13-0/+3
| | | | | | | | | | | | | | For FSL low-end processors (VVN2.2), in order to detect the SD card, we should enable PEREN, HCKEN and IPGEN to enable the clock. Otherwise, after booting the u-boot, and then inserting the SD card, the SD card can't be detected. For SDHC VVN2.3 IP, these bits are reserved, and SDCLKEN is used. And when accessing to these reserved bit, no any impact happened. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> CC: Andy Fleming <afleming@gmail.com> CC: Marek Vasut <marex@denx.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
* i.MX: fsl_esdhc: allow use with cache enabled.Eric Nelson2012-07-13-1/+16
| | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: fsl_esdhc: Poll until card is not busy anymoreDirk Behme2012-05-08-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch imports parts of two patches from the Freescale U-Boot with the following commit messages: ENGR00156405 ESDHC: Add workaround for auto-clock gate errata ENGcm03648 http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/drivers/mmc/imx_esdhc.c?h=imx_v2009.08_12.01.01&id=e436525a70fe47623d346bc7d9f08f12ff8ad787 The errata, not applicable to USDHC, causes ESDHC to shut off clock to the card when auto-clock gating is enabled for commands with busy signalling and no data phase. The card might require the clock to exit the busy state, so the workaround is to disable the auto-clock gate bits in SYSCTL register for such commands. The workaround also entails polling on DAT0 bit in the PRSSTAT register to learn when busy state is complete. Auto-clock gating is re-enabled at the end of busy state. ENGR00156670-1 ESDHC/USDHC: Remove delay before each cmd and some bug fixes http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/drivers/mmc/imx_esdhc.c?h=imx_v2009.08_12.01.01&id=a77c6fec8596891be96b2cdbc742c9824844b92a Removed delay of 10 ms before each command. There should not be a need to have this delay after the ENGR00156405 patch that polls until card is not busy anymore before proceeding to next cmd. This patch imports the polling part of both patches. The auto-clock gating code don't apply for i.MX6 as implemented in these two patches. SYSCTL_RSTA was defined twice. Remove one definition. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Andy Fleming <afleming@freescale.com> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Stefano Babic <sbabic@denx.de>
* fsl_esdhc: fix PIO mode transfersIra Snyder2012-01-08-1/+2
| | | | | | | | | | | | | | | | The pointer to the registers used to control the Freescale ESDHC MMC controller is not initialized correctly when using PIO mode. This is fixed by initializing the pointer in the same way as all other sites within the driver. Examining the commit history shows that this was broken at introduction due to a code change in upstream U-Boot to support the mx51 processor family. Reported-by: Jim Lentz <JLentz@zhone.com> Cc: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
* mmc: fsl_esdhc: Implement card-detect hook.Thierry Reding2012-01-08-17/+12
| | | | | | | | | | | | | | | | This card-detect hook probably doesn't work. Perhaps somebody with more knowledge about the hardware can comment on this. I think that perhaps even the complete code from esdhc_init() could go into the getcd() function instead or mmc_getcd() needs to be called at some later time after mmc_init(), which, however, would require many other drivers to change. In addition to implementing the hook, this patch also removes the call to the board_mmc_getcd() function which is now called from the MMC framework and is no longer required here. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Jason Liu <jason.hui@linaro.org>
* mmc: Change board_mmc_getcd() function prototype.Thierry Reding2012-01-08-3/+5
| | | | | | | | | | | | | | | | | | | | | The new API no longer uses the extra cd parameter that was used to store the card presence state. Instead, this information is returned via the function's return value. board_mmc_getcd() returns -1 to indicate that no card-detection mechanism is implemented; 0 indicates that no card is present and 1 is returned if it was detected that a card is present. The rationale for this change can be found in the following email thread: http://lists.denx.de/pipermail/u-boot/2011-November/110180.html In summary, the old API was not consistent with the rest of the MMC API which always passes a struct mmc as the first parameter. Furthermore the cd parameter was used to mean "card absence" in some implementations and "card presence" in others. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Jason Liu <jason.hui@linaro.org>
* i.mx: fsl_esdhc: add the i.mx6q supportJason Liu2012-01-08-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mmc host controller on the i.mx6q is called usdhc which is redesigned based on the freescale esdhc controller. The usdhc controller is almost compatible with esdhc except it adds one mix register to support debug/SD3.0 and move the low bit 0-6 of XFERTYP register to the mix control reg low bit 0-6. Thus on i.mx6q, we have the following compared with the previous soc: (can refer to RM of chapter 56.3.3) i.mx6q: mix control: bit 31 - bit 7: Added for debug/SD3.0 support bit 6 - bit 0: move in the XFERTYP register bit 6-0 on previous soc XFERTYP register: bit 31 - bit 7: the same as before, bit 6 - bit 0: no-use previous soc mix control: no XFERTYP register: bit 31 - bit 0: xfertype information Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc: Andy Fleming <afleming@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* fsl_esdhc: Initialize mmc->b_maxFabio Estevam2011-05-18-0/+1
| | | | | | | commit 262951(MMC: make b_max unconditional) missed to update fsl_esdhc. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* fsl_esdhc: Fix multi-block read restriction on i.MX53 eSDHCv2Jason Liu2011-04-29-0/+4
| | | | | | | | | | | | | | | | | | | | For freescale i.MX53 eSDHCv2, when using CMD12, cmdtype need to be set to ABORT, otherwise, next read command will hang. This is a software Software Restrictions in i.MX53 reference manual: 29.7.8 Multi-block Read For pre-defined multi-block read operation, that is,the number of blocks to read has been defined by previous CMD23 for MMC, or pre-defined number of blocks in CMD53 for SDIO/SDCombo,or whatever multi-block read without abort command at card side, an abort command, either automatic or manual CMD12/CMD52, is still required by ESDHC after the pre-defined number of blocks are done, to drive the internal state machine to idle mode. In this case, the card may not respond to this extra abort command and ESDHC will get Response Timeout. It is recommended to manually send an abort command with RSPTYP[1:0] both bits cleared. Signed-off-by: Jason Liu <jason.hui@linaro.org>
* drivers/mmc/fsl_esdhc.c: reordered testsFrans Meulenbroeks2011-04-13-3/+3
| | | | | | | | | | | | As DATA_ERROR includes the value IRQSTAT_DTOE, a timeout error would yield the first error return instead of TIMEOUT. By swapping the test TIMEOUTs are reported as such An alternate solution would be to remove the IRQSTAT_DTOE from the DATA_ERROR define but as that one might be less desired I've opted for the simplest solution Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fsl_esdhc: Deal with watermark level register related changesPriyanka Jain2011-04-10-4/+4
| | | | | | | | | | | | | P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Correcting esdhc timeout counter calculationPriyanka Jain2011-03-07-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | - Timeout counter value is set as DTOCV bits in SYSCTL register For counter value set as timeout, Timeout period = (2^(timeout + 13)) SD Clock cycles - As per 4.6.2.2 section of SD Card specification v2.00, host should cofigure timeout period value to minimum 0.25 sec. - Number of SD Clock cycles for 0.25sec should be minimum (SD Clock/sec * 0.25 sec) SD Clock cycles = (mmc->tran_speed * 1/4) SD Clock cycles - Calculating timeout based on (2^(timeout + 13)) >= mmc->tran_speed * 1/4 Taking log2 both the sides and rounding up to next power of 2 => timeout + 13 = log2(mmc->tran_speed/4) + 1 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Mingkai Hu <Mingkai.Hu@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)Kumar Gala2011-02-03-0/+5
| | | | | | | Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8, and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)Roy Zang2011-01-14-0/+5
| | | | | | | | | | | The default value of the SRS, VS18 and VS30 and ADMAS fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one. Clear these bits out when we read HOSTCAPBLT. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)Jerry Huang2011-01-14-1/+9
| | | | | | | | | Do not issue a manual asynchronous CMD12. Instead, use a (software) synchronous CMD12 or AUTOCMD12 to abort data transfer. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Fix esdhc disabled problem on some platformsChenhui Zhao2011-01-14-6/+8
| | | | | | | | | | | | Some new platform's esdhc pins don't share with other function. The eSDHC shouldn't be disabled, even if "esdhc" isn't defined in hwconfig env variable. Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem. Signed-off-by: Chenhui Zhao <b26998@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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