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path: root/drivers/mmc/dw_mmc.c
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* mmc: dw_mmc: support fifo mode in dwc mmc driverhuang lin2015-12-01-18/+67
| | | | | | | | some soc(rk3036 etc) use dw_mmc but do not have internal dma, so we implement fifo mode to read and write data. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* mmc: dw_mmc: move data transfer as a separate functionhuang lin2015-12-01-28/+37
| | | | | | | | the data transfer seem to long in the dwmci_send_cmd function, so move this block as a separate funciton. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* driver: dwmmc: Fix pointer conversion warnings for hikeyPrabhakar Kushwaha2015-11-12-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix below compilation warings happening for hikey_defconfig drivers/mmc/dw_mmc.c: In function ‘dwmci_set_idma_desc’: drivers/mmc/dw_mmc.c:43:20: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac); ^ drivers/mmc/dw_mmc.c: In function ‘dwmci_prepare_data’: drivers/mmc/dw_mmc.c:61:35: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac); ^ drivers/mmc/dw_mmc.c:73:9: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] (u32)bounce_buffer + (i * PAGE_SIZE)); ^ CC drivers/mmc/hi6220_dw_mmc.o drivers/mmc/hi6220_dw_mmc.c: In function ‘hi6220_dwmci_add_port’: drivers/mmc/hi6220_dw_mmc.c:51:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] host->ioaddr = (void *)regbase; Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* mmc: dw_mmc: Increase timeout to 4 minutes (as in Linux kernel)Łukasz Majewski2015-09-28-1/+1
| | | | | | | | | | | | | | | | | | | | The commit: d9dbb97be0e4a550457aec5f11afefb446169c90 "mmc: dw_mmc: Zap endless timeout" removed endless loop waiting for end of dw mmc transfer. For some workloads - dfu test @ Odroid XU3 (sending 8MiB file) - and SD cards (e.g. MicroSD Kingston 4GiB, Adata 4GiB) the default timeout is to short. The new value - 4 minutes (240 seconds) - is the same as the one used in Linux kernel driver. Such fix should be good enough until we come up with better fix for this issue. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
* Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h headerSimon Glass2015-09-11-0/+1
| | | | | | | Now that we have a new header file for cache-aligned allocation, we should move the stack-based allocation macro there also. Signed-off-by: Simon Glass <sjg@chromium.org>
* mmc: Support bypass mode with the get_mmc_clk() methodSimon Glass2015-09-02-1/+1
| | | | | | | | | Some SoCs want to adjust the input clock to the DWMMC block as a way of controlling the MMC bus clock. Update the get_mmc_clk() method to support this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
* dw_mmc: Calculate dwmmc FIFO threshold size if not providedSimon Glass2015-08-13-2/+8
| | | | | | | | | We can calculate this. Add code to do this if it is not provided. panto: prefix changed to dw_mmc to make things easier to grep Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: dw_mmc: Avoid using printf() for errorsSimon Glass2015-08-11-11/+12
| | | | | | | | | | | | | The dw_mmc driver uses printf() in various places. These bloat the code and cause problems for SPL. Use debug() where possible and try to return a useful error code instead. panto: Small rework to make it apply against top of tree. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: dw_mmc: Improve handling of data transfer failureMarek Vasut2015-08-11-7/+9
| | | | | | | | | | | In case the data transfer failure happens, instead of returning immediatelly, make sure the DMA is disabled, status register is cleared and the bounce buffer is stopped. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
* mmc: dw_mmc: Zap endless timeoutMarek Vasut2015-08-11-2/+17
| | | | | | | | | | Endless timeouts are bad, since if we get stuck in one, we have no way out. Zap this one by implementing proper timeout. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
* mmc: dw_mmc: Stop bounce buffer even in case of failureMarek Vasut2015-08-11-0/+1
| | | | | | | | | | | | The driver didn't stop the bounce buffer in case a data transfer failed. This would lead to memory leakage if the communication between the CPU and the card is unreliable. Add the missing call to stop the bounce buffer. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
* mmc: remove the MMC_MODE_HC flagRob Herring2015-05-05-1/+1
| | | | | | | | | | | | | High capacity support is not a host capability, but a device capability that is queried via the OCR. The flag in the operating conditions request argument can just be set unconditionally. This matches the Linux implementation. [panto] Hand merged and renumbering MMC_MODE_DDR_52MHz. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
* mmc: dw_mmc: fixed the wrong bit controlJaehoon Chung2015-02-23-1/+1
| | | | | | If mode is not DDR-mode, then it needs to clear it. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: dw_mmc: Use active DDR mode flagAndrew Gabbasov2014-12-12-1/+1
| | | | | | | The card_caps bit should denote the card capability to use DDR mode, but we need the flag indicating that the DDR mode is active. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
* mmc: dw_mmc: cleanupsPavel Machek2014-10-06-12/+22
| | | | | | | | | | | | | | | | | The dw_mmc driver was responding to errors with debug(). Change that to prinf()/puts() respectively so that any errors are immediately obvious. Also adjust english in comments. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Acked-by: Chin Liang See <clsee@altera.com>
* mmc/dw_mmc: Fix clock divider calculation error for bypass modeChin Liang See2014-08-01-1/+4
| | | | | | | | | | | | To fix the clock divider calculation error when the controller clock same as the operating frequency. This is known as bypass mode. In this mode, the divider should be 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Mischa Jonker <mjonker@synopsys.com>
* mmc: dw_mmc: support the DDR modeJaehoon Chung2014-05-16-2/+10
| | | | | | | | | Support the DDR mode at dw-mmc controller Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* mmc: Split mmc struct, rework mmc initialization (v2)Pantelis Antoniou2014-03-24-29/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way that struct mmc was implemented was a bit of a mess; configuration and internal state all jumbled up in a single structure. On top of that the way initialization is done with mmc_register leads to a lot of duplicated code in drivers. Typically the initialization got something like this in every driver. struct mmc *mmc = malloc(sizeof(struct mmc)); memset(mmc, 0, sizeof(struct mmc); /* fill in fields of mmc struct */ /* store private data pointer */ mmc_register(mmc); By using the new mmc_create call one just passes an mmc config struct and an optional private data pointer like this: struct mmc = mmc_create(&cfg, priv); All in tree drivers have been updated to the new form, and expect mmc_register to go away before long. Changes since v1: * Use calloc instead of manually calling memset. * Mark mmc_register as deprecated. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: Convert mmc struct's name array to a pointerPantelis Antoniou2014-03-24-1/+1
| | | | | | | Using an array is pointless; even more pointless (and scary) is using sprintf to fill it without a format string. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: Remove ops from struct mmc and put in mmc_opsPantelis Antoniou2014-03-24-3/+7
| | | | | | | | | | | | | | | | | Remove the in-structure ops and put them in mmc_ops with a constant pointer to it. This makes the mmc structure smaller as well as conserving code space (in theory). All in-tree drivers are converted as well; this is done in a single patch in order to not break git bisect. Changes since V1: Fix compilation b0rked issue on omap platforms where OMAP_GPIO was not set. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* MMC: DWMMC: Correct the CLKDIV register valueRajeshwari S Shinde2014-02-07-1/+1
| | | | | | | | | | | | | | | | | | This patch corrects the divider value written to CLKDIV register. Since SDCLKIN is divided inside controller by the DIVRATIO value set in the CLKSEL register, we need to use the same output clock value to calculate the CLKDIV value. as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) Input parameter to mmc_clk is changed to dwmci_host, since we need the same to read DWMCI_CLKSEL register. This improves the read timing values for channel 0 on SMDK5250 from 0.288sec to 0.144sec Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: dwmmc: mode change to 0644Minkyu Kang2014-01-14-0/+0
| | | | | | Don't know why but, file permission was changed Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* mmc/dwmmc: use bounce buffer for data exchange between CPU and MMC controllerAlexey Brodkin2014-01-09-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bounce buffer implementation takes care of proper data buffer alignemt and correct flush/invalidation of data cache at once so we no longer depend on input data variety and make sure CPU and MMC controller deal with expected data in case of enabled data cache. Bounce buffer requires to add its definition (CONFIG_BOUNCE_BUFFER) in board configuration, otherwise corresponding library won't be compiled and linker will fail to build resulting executable. Difference since v1 - fixed compile-time warning with type casting to "void *": Slight edit to remove UTF8 characters in the commit message. Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> ==== passing argument 2 of 'bounce_buffer_start' discards 'const' qualifier from pointer target type ==== Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Alim Akhtar <alim.akhtar@samsung.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Amar <amarendra.xt@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Andy Fleming <afleming@gmail.com>
* mmc/dwmmc: Using calloc instead mallocChin Liang See2014-01-08-2/+2
| | | | | | | | | | | | | | | To enhance the SDMMC DesignWare driver to use calloc instead of malloc. This will avoid the incident that uninitialized members of mmc structure are later used for NULL comparison. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Andy Fleming <afleming@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc/dwmmc: modify FIFO threshold only if value explicitly setAlexey Brodkin2013-12-08-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | If platform provides "host->fifoth_val" it will be used for initialization of DWMCI_FIFOTH register. Otherwise default value will be used. This implementation allows: * escape unclear and recursive calculations that are currently in use * use whatever custom value for DWMCI_FIFOTH initialization if any particular SoC requires it Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Alim Akhtar <alim.akhtar@samsung.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Amar <amarendra.xt@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Andy Fleming <afleming@freescale.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: dw_mmc: remove the exynos specific code in dw-mmc.cJaehoon Chung2013-12-08-10/+2
| | | | | | | | | | | dw-mmc.c is the general driver file. So, remove the exynos specific code at dw-mmc.c. Instead, exynos specific cod can be move into exynos-dw_mmc.c. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* DWMMC: SMDK5420: Disable SMU for eMMCRajeshwari Shinde2013-10-31-0/+11
| | | | | | | | | | | | SMDK5420 has a new Security Management Unit added for dwmmc driver, hence, configuring the control registers to support booting via eMMC. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: dw_mmc: change the callback function name.Jaehoon Chung2013-10-31-3/+3
| | | | | | | | To prevent the confusion, use the get_mmc_clk() instead of mmc_clk(). get_mmc_clk() is more exactly name. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc/dw_mmc: Allocate the correct amount of descriptorsMischa Jonker2013-09-20-2/+2
| | | | | | | | | | | | | This fixes two issues: * a descriptor was allocated for every block, while a descriptor can take 8 blocks * there was an off-by-one error in the descriptor preparation: there were two last descriptors, one with length==0 Signed-off-by: Mischa Jonker <mjonker@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Andy Fleming <afleming@gmail.com>
* mmc/dw_mmc: Fix DMA descriptor corruptionMischa Jonker2013-09-20-3/+4
| | | | | | | | | | | | | | | | | | | In dwmci_prepare_data, the descriptors are allocated for DMA transfer. These are allocated using the ALLOC_CACHE_ALIGN_BUFFER. This macro uses the stack to allocate these descriptors. This becomes a problem if the DMA transfer continues after the processor leaves the function in which the descriptors were allocated. Therefore, I have moved the allocated of the buffers up one level, to dwmci_send_cmd(). The DMA transfer should be complete when leaving this function. Signed-off-by: Mischa Jonker <mjonker@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Andy Fleming <afleming@gmail.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-14/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* drivers/mmc/dw_mmc - remove extra arch specific "asm/arch/clk.h" inclusionAlexey Brodkin2013-07-16-1/+0
| | | | | | | | | | | | | | | | | | 1. No contents of "asm/arch/clk.h" is used within "dw_mmc.c". 2. If arch doesn't have "asm/arch/clk.h" driver won't build. Without mentioned inclusion dw_mmc driver could be built for arches other than ARM. For ARM driver still builds without it. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Amar <amarendra.xt@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* MMC: DWMMC: Fix FIFO_DEPTH calculationRajeshwari Shinde2013-06-17-8/+6
| | | | | | | | | | | | | | | | | | | | Current DWMMC driver used to give FIFO underrun/overrun error every 3rd time for mmc rescan command. In current code FIFO_DEPTH is getting calculated after reading the default FIFOTH register and extracting the RX_WMARK bits from it i.e (RX_WMARK = FIFO_DEPTH/2 -1). Instead of storing the correct value, we were recalculating the FIFO_DEPT each time which is not correct. Based on "[PATCH V9 3/9] DWMMC: Initialise dwmci and resolve EMMC read write issues" http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/160247 Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* DWMMC: Initialise dwmci and resolve EMMC read write issuesAmar2013-06-13-9/+12
| | | | | | | | | | | | This patch enumerates dwmci and set auto stop command during dwmci initialisation. EMMC read/write is not happening in current implementation due to improper fifo size computation. Hence modified the fifo size computation to resolve EMMC read write issues. Signed-off-by: Amar <amarendra.xt@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* mmc: dw-mmc: support DesignWare MMC ControllerJaehoon Chung2012-10-22-0/+385
Support the DesginWare MMC Controller. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Rajeshawari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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