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* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-10-26-3/+0
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| * arm: Remove support for lpc2292Marek Vasut2012-10-26-3/+0
| | | | | | | | | | | | This stuff has been rotting in the tree for a year now. Remove it. Signed-off-by: Marek Vasut <marex@denx.de>
* | drivers/i2c/fsl_i2c.c: sparse fixKim Phillips2012-10-25-1/+1
|/ | | | | | | fsl_i2c.c:217:14: warning: symbol 'get_i2c_clock' was not declared. Should it be static? Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Heiko Schocher <hs@denx.de>
* i2c: sh_i2c: use setbits/clrbits macroTetsuyuki Kobayashi2012-10-16-4/+4
| | | | | | | Use setbits/clrbits macro when read-modify-write register. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* i2c: sh_i2c.c: check error in i2c_read and i2c_writeTetsuyuki Kobayashi2012-10-16-18/+32
| | | | | | | | Before this patch, i2c_{read,write} always returned 0. Check TACK in i2c_raw_{read,write} so that i2c_{read,write} return non-zero when error. Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
* i2c: sh_i2c: enable i2c_probeTetsuyuki Kobayashi2012-10-16-5/+27
| | | | | | | | | Before this patch i2c_probe() always returned 0 and "i2c probe" command did not work properly. Modify i2c_set_addr() to check TACK when waiting DTE and make i2c_probe() call this function. Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
* i2c: sh_i2c.c: support I2C2, I2C3 and I2C4Tetsuyuki Kobayashi2012-10-16-0/+15
| | | | | | | sh_i2c.c support I2C0 and I2C1. This patch extends it to I2C4. Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
* i2c: sh_i2c.c: adjust for SH73A0Tetsuyuki Kobayashi2012-10-16-0/+4
| | | | | | | | Adjust i2c_raw_read() in sh_i2c.c to work for SH73A0. After this patch, "i2c md" and "i2c mw" command on U-Boot work properly on KZM-A9-GT board. Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
* i2c: sh_i2c.c: correct BUSY bit define in ICSRTetsuyuki Kobayashi2012-10-16-1/+1
| | | | | | | Correct BUSY bit define in ICSR from (1<<3) to (1<<4). Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
* i2c: sh_i2c.c: support iccl and icch extensionTetsuyuki Kobayashi2012-10-16-8/+22
| | | | | | | | R-mobile SoC (at least SH73A0) has extension bits to store 8th bit of iccl and icch. This patch add support for the extentin bits. Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
* imx: Use MXC_I2C_CLK in imx i2c driverMatthias Weisser2012-10-15-2/+2
| | | | | | | | i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using MXC_I2C_CLK on all imx systems using i2c. Signed-off-by: Matthias Weisser <weisserm@arcor.de> Acked-by: Stefano Babic <sbabic@denx.de>
* Tegra20: Move some include files to arch-tegra for sharing with Tegra30Tom Warren2012-10-15-2/+2
| | | | | | | | | | | The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by: Tom Warren <twarren@nvidia.com>
* i2c: sh: Remove irq_wait functionNobuhiro Iwamatsu2012-10-03-16/+0
| | | | | | | irq_wait function is not referred to from anywhere. Reported-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-09-21-6/+6
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| * Tegra: Change Tegra20 to Tegra in common code, prep for T30Tom Warren2012-09-10-6/+6
| | | | | | | | | | | | | | | | | | | | Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate. Convert tegra20_ source file and function names to tegra_, also. Upcoming Tegra30 port will use common code/defines/names where possible. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* | omap4 i2c: add support for i2c bus 4Koen Kooi2012-09-06-0/+8
|/ | | | Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
* mxs: Convert sys_proto.h prefixes to 'mxs'Otavio Salvador2012-09-01-1/+1
| | | | | | | The sys_proto.h functions (except the boot modes) are compatible with i.MX233 and i.MX28 so we use 'mxs' prefix for its methods. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* tegra20: rename tegra2 -> tegra20Allen Martin2012-09-01-6/+6
| | | | | | | | | | This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mxs: prefix register structs with 'mxs' prefixOtavio Salvador2012-09-01-6/+6
| | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* omap24xx_i2c: add 2-byte address supportIlya Yanok2012-09-01-32/+26
| | | | | | | | | | | | | | | Various devices like EEPROMs require 2-byte address support to be properly accessed. This patch adds this support for OMAP2/3/4 I2C controller driver. I've tested it with EEPROM (16 bit address) and TPS65217 chip (8 bit address) on TI Beaglebone board. Unfortunately I don't have access to any compatible hardware with 16bit data register so I can't test if those #ifdef clauses really work. CC: Tom Rini <trini@ti.com> Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* I2C: Add support for Multi channelRajeshwari Shinde2012-07-31-0/+27
| | | | | | | | This adds multiple i2c channel support for I2C. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* I2C: Modify the I2C driver for EXYNOS5Rajeshwari Shinde2012-07-31-77/+117
| | | | | | | | | | | | | | | | | | | This patch modifies the S3C I2C driver to suppport EXYNOS5. The cahnges made to driver are as follows: - I2C base address is passed as a parameter to many functions to avoid multiple #ifdef - Channel initialisation is moved to a commom funation as it is required by i2c_init. - Hardcoding for I2CCON_ACKGEN removed. - Replaced printf with debug. - Checkpatch issues resolved. - Pinmux setting will be done in board/samsung/smdk5250/smdk5250.c to avoid repeated setting of gpio lines, as it have multi bus support. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* I2C: Move struct s3c24x0_i2c to a common place.Rajeshwari Shinde2012-07-31-0/+33
| | | | | | | | | | struct s3c24x0_i2c is being moved to common local header file so that the same can be used by s3c series and exynos series SoCs. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* mxc_i2c: finish adding CONFIG_I2C_MULTI_BUS supportTroy Kisky2012-07-31-0/+17
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: add bus recovery supportTroy Kisky2012-07-31-0/+26
| | | | | | | | | Add support for calling a function that will toggle the SCL line to return the bus to idle condition. The actual toggling function is added in a later patch. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: prep work for multiple busses supportTroy Kisky2012-07-31-21/+104
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: add i2c_regs argument to i2c_imx_stopTroy Kisky2012-07-31-12/+7
| | | | | | | This is prep work for CONFIG_I2C_MULTI_BUS. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: add retriesTroy Kisky2012-07-31-9/+27
| | | | | | | Retry unexpected hardware errors. This will not retry a received NAK. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: check for arbitration lostTroy Kisky2012-07-31-0/+7
| | | | | | | No need to continue waiting if arbitration lost. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: change slave addr if conflicts with destination.Troy Kisky2012-07-31-0/+2
| | | | | | | The i2c controller cannot be both master and slave in the same transaction. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: don't disable controller after every transactionTroy Kisky2012-07-31-15/+13
| | | | | | | This helps in a multiple bus master environment which is why I also added a wait for bus idle. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: place i2c_reset code inlineTroy Kisky2012-07-31-12/+3
| | | | | | | | imx_reset is only referenced once so move to that location. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: place imx_start code inlineTroy Kisky2012-07-31-33/+20
| | | | | | | | imx_start is only referenced once so move to that location. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: remove redundant readTroy Kisky2012-07-31-1/+0
| | | | | | | | wait_for_sr_state returns i2sr on success so no need to read again. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: combine i2c_imx_bus_busy and i2c_imx_trx_complete into ↵Troy Kisky2012-07-31-51/+29
| | | | | | | | | | | | | | | | | | | | wait_for_sr_state Not using udelay gives a more accurate timeout. The current implementation of udelay in imx-common does not seem to wait at all for a udelay(1). Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> ---- V2: Added WATCHDOG_RESET as suggested by Marek Vasut add error message when stop fails mxc_i2c: code i2c_probe as a 0 length i2c_write Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_i2c.c: code i2c_probe as a 0 length i2c_writeTroy Kisky2012-07-31-17/+8
| | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_i2c: call i2c_imx_stop on error in i2c_read/i2c_writeTroy Kisky2012-07-31-3/+7
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: create i2c_init_transferTroy Kisky2012-07-31-26/+18
| | | | | | | | | Initial code of i2c_read and i2c_write is identical, move to subroutine. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_i2c: clear i2sr before waiting for bitTroy Kisky2012-07-31-4/+5
| | | | | | | | | | | Let's clear the sr register before waiting for bit to be set, instead of clearing it after hardware sets it. No real operational difference here, but allows combining of i2c_imx_trx_complete and i2c_imx_bus_busy in later patches. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: create tx_byte functionTroy Kisky2012-07-31-58/+24
| | | | | | | | Use tx_byte function instead of having 3 copies of the code. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: remove ifdef of CONFIG_HARD_I2CTroy Kisky2012-07-31-5/+1
| | | | | | | | This is always selected when CONFIG_I2C_MXC is selected, so it adds no value. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: fix i2c_imx_stopTroy Kisky2012-07-31-1/+1
| | | | | | | | | | Instead of clearing 2 bits, all the other bits were set because '|=' was used instead of '&='. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxs-i2c: Fix internal address byte orderTorsten Fleischer2012-07-11-1/+1
| | | | | | | | | | | | | | | | | | Large EEPROMs, e.g. 24lc32, need 2 byte to address the internal memory. These devices require that the high byte of the internal address has to be written first. The mxs_i2c driver currently writes the address' low byte first. The following patch fixes the byte order of the internal address that should be written to the I2C device. Signed-off-by: Torsten Fleischer <to-fleischer@t-online.de> CC: Marek Vasut <marex@denx.de> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_i2c: remove setting speed at each startTroy Kisky2012-07-11-6/+0
| | | | | | | | | | | | Other then being very weird, this code was also wrong. For example, say I set speed to 100K. I'll read back the speed as 85937. But the speed is really 85937.5, so we I reset the speed to 85937, I'll get 73660.7. After a couple of transactions my speed is now exactly 68750 so it will remain there. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_i2c: specify i2c base address in config fileTroy Kisky2012-07-11-21/+4
| | | | | | | | | The following platforms had their config files changed flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd and mx53loco. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* i2c: designware_i2c.c: Add support for the "i2c probe" commandStefan Roese2012-07-07-6/+10
| | | | | | | | | | | | | | | i2c_probe() is changed to reinit the i2c bus upon read failure. This is naturally the case upon i2c bus probing. Also, some printf messages upon read failure are removed. As they would interfere with the "i2c probe" command. Additionally, i2c_set_bus_speed() now returns 0, so that the "i2c speed" command can be used. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Amit Virdi <amit.virdi@st.com> Cc: Vipin Kumar <vipin.kumar@st.com>
* omap24xx_i2c: Add AM33XX supportTom Rini2012-07-07-3/+3
| | | | | | | | | The same places that check for CONFIG_OMAP44XX need to check for CONFIG_AM33XX as we share the same i2c block. Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
* Revert "I2C: OMAP: detect more devices when probing an i2c bus"Tom Rini2012-07-07-11/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 0e57968a215d1b9d271f3fa5bebeddeaea0c8075. The short version of the original commit is that some i2c devices cannot be probed via read as they NAK the first cycle, so try and probe via a write that we abort before it writes to the device. This however is not allowed by the TRM for any of these parts. The section on I2C_CON (table 17-35 I2C_CON for am/dm37x for example) says you must not change the register while STT has been set. On these parts, the unpredictable behavior that the chip exhibits is not problematic. On OMAP4 however it results in the chip being in a bad state: Panda # i2c probe Valid chip addresses: 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Panda # i2c md 50 0 timed out in wait_for_pin: I2C_STAT=0 I2C read: I/O error Error reading the chip. We must revert the original behavior to bring probe back into line with the TRM. Cc: Nick Thompson <nick.thompson@ge.com> Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
* tegra: i2c: Add function to find DVC busSimon Glass2012-05-15-0/+14
| | | | | | | | Add tegra_i2c_get_dvc_bus_num() to obtain the I2C bus number of DVC bus. This allows us to talk to the PMU. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* i2c:designware Turn off the ctrl when setting the speedArmando Visconti2012-04-24-0/+11
| | | | | | | | | | The designware i2c controller must be turned off before setting the speed in IC_CON register, as stated in the section 6.3.1 of the dw_apb_i2c_db.pdf. Signed-off-by: Michel Sanches <michel.sanches@st.com> Signed-off-by: Armando Visconti <armando.visconti@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com>
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