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* i2c: rcar_i2c: Fix order of restart and clear statusNobuhiro Iwamatsu2014-11-10-2/+2
| | | | | | | | | | In case of repeated START condition, the restart has to be kicked before clear status (MSR register). If it is kicked after clear status, R-Car I2C may transfer data (TXD register) or receive data (RXD register) instead of transferring slave address (MAR register). Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* drivers/i2c/fsl_i2c: Change CONFIG_I2C_TIMEOUT to 100msShaveta Leekha2014-11-10-1/+1
| | | | | | | | | | | | | | Some slow I2C devices like Power Monitor(ZM7304) at times do not work well with low timeout value, so I2C bus get stuck during read cycle with this device, changing it to 100ms from 10ms works fine A lot of other i2c drivers like mxc and i2c drivers of BOOTROM also use relax timeouts to give sufficient ticks to work well with slower devices Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
* ppc4xx: Handle i2c stuck on combined xferDirk Eibach2014-11-10-0/+21
| | | | | | | | | | | | ppc4xx i2c master gets stuck on errors while repeated start is active. Can be easily reproduced by "i2c md" on an unpopulated i2c address. There is not stop condition given, scl remains pulled low. The only way out seems to be doing a stop manually and then a soft reset. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix i2c repeated startDirk Eibach2014-11-10-4/+5
| | | | | | | | | | | | | Debugging some i2c trouble I saw on my scope that repeated start is not working properply. The 4xx even held clock pulled down after transfers. Having a look in the driver I realized that IIC_CNTL_RPST is set on that part of the transfer that should begin with a repeated start. But repeated start is about not sending a stop condition, so IIC_CNTL_RPST has to be set on the last transfer before the repeated start happens. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: use __weakJeroen Hofstee2014-11-04-6/+2
| | | | | Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* i2c: designware: Convert driver to multibus/multiadapter frameworkStefan Roese2014-10-29-167/+128
| | | | | | | | | | | | | | | | | | | | | In preparation for the SoCFPGA support of the designware I2C driver, convert this driver to the common CONFIG_SYS_I2C framework. This patch converts all users of this driver, this is: - ST spearxxx boards - AXS101 (ARC700 platform) I couldn't test this patch on those boards. Only compile tested for all spear boards. And tested on SoCFPGA. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Tested-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Heiko Schocher <hs@denx.de> Cc: Vipin Kumar <vk.vipin@gmail.com> Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
* i2c: mxs: Add support for I2C 1 on i.MX28Marek Vasut2014-10-29-1/+8
| | | | | | | | Add support for I2C bus 1 on the i.MX28. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de>
* i2c: mxs: Pass the i2c_adapter aroundMarek Vasut2014-10-29-67/+67
| | | | | | | | | | | | This patch permeates the struct i2c_adapter throughout the driver, so that it can be used to determine which adapter should be used. Note that the driver still supports only one adapter. Note that the patch does shuffle mxs_i2c_set_bus_speed() to the top of the driver, but the function remains unchanged. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de>
* i2c: mxs: Add basic support for i2c frameworkMarek Vasut2014-10-29-21/+30
| | | | | | | | | | | This patch just converts the function prototypes used throughout this driver to match those of the i2c framework. There is so far no functional change. This patch does not do the deeper integration of the framework bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de>
* i2c: mxs: Consolidate hard-coded bus addressMarek Vasut2014-10-29-7/+12
| | | | | | | | | | This patch prepares the MXS I2C driver for the conversion to the new I2C driver framework by pulling out the hard-coded I2C0 address from all the places. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de>
* i2c: designware: add an implement i2c protosJeroen Hofstee2014-10-25-7/+12
| | | | | | | | | | | Include the i2c header and change the non confirming functions to do so. Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Acked-by: Heiko Schocher <hs@denx.de> [trini: Fix i2c_get_bus_num prototype] Signed-off-by: Tom Rini <trini@ti.com>
* tegra: make local functions staticJeroen Hofstee2014-10-25-3/+4
| | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* i2c: mvtwsi: Add support for Marvell Armada XPStefan Roese2014-10-23-1/+1
| | | | | | | | To support the Armada XP SoC, we just need to include the correct header. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Luka Perkov <luka@openwrt.org>
* arm: marvell: Move arch/kirkwood.h to arch/soc.hStefan Roese2014-10-23-1/+1
| | | | | | | | | This move makes is possible to use this header not only from kirkwood platforms but from all Marvell mvebu platforms. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
* cosmetic: replace MIN, MAX with min, maxMasahiro Yamada2014-09-24-2/+2
| | | | | | | The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kconfig: add blank Kconfig filesMasahiro Yamada2014-09-24-0/+0
| | | | | | | | This would be useful to start moving various config options. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* ls102xa: i2c: Add i2c support for LS102xAWang Huan2014-09-08-2/+2
| | | | | | | | | | | The existing i.MX's I2C driver mxc_i2c.c is compatible with the controller of LS102xA. As I2C's registers are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to use 8-bit driver. This patch is to add I2C 1,2,3 support for LS102xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-28-39/+51
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| * sunxi: Add i2c supportHans de Goede2014-07-18-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the i2c controller found on all Allwinner sunxi SoCs, this is the same controller as found on the Marvell orion5x and kirkwood SoC families, with a slightly different register layout, so this patch uses the existing mvtwsi code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-By: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Heiko Schocher <hs@denx.de> [ ijc -- updated u-boot-spl-fel.lds ]
| * mvtwsi: convert to CONFIG_SYS_I2C frameworkHans de Goede2014-07-16-39/+33
| | | | | | | | | | | | | | | | | | | | | | | | Note this has only been tested on Allwinner sunxi devices (support for which gets introduced by a later patch). The kirkwood changes have been compile tested using the wireless_space board config, the orion5x changes have been compile tested using the edminiv2 board config. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Heiko Schocher <hs@denx.de>
* | fsl_i2c: add support for 3rd and 4th I2CShengzhou Liu2014-07-16-2/+20
| | | | | | | | | | | | Add support for 3rd and 4th I2C. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | i2c, omap24xx: add i2c deblock sequenzHeiko Schocher2014-07-16-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a bus busy is detected when intializing the driver, toggle 9 times the scl pin. Therefore enable the test mode of the controller, in which the scl, sda pins can be controlled manually. Tested on the siemens boards pxm2, rut and dxr2. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Hannes Petermaier <oe5hpm@oevsv.at> Cc: Lubomir Popov <lpopov@mm-sol.com> Cc: Steve Sakoman <steve@sakoman.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Vincent Stehlé <v-stehle@ti.com> Cc: Samuel Egli <samuel.egli@siemens.com>
* | board: gdsys: Make gdsys osd hardware detection more robustDirk Eibach2014-07-07-1/+0
| | | | | | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | i2c: IHS I2C master driverDirk Eibach2014-07-07-0/+205
| | | | | | | | | | | | | | | | IHS I2C master support was merely a hack in the osd driver. Now it is a proper u-boot I2C framework driver, supporting the v2.00 master features. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2014-07-07-17/+27
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| * i2c: tegra: dump alen in debug statementsStephen Warren2014-07-03-4/+4
| | | | | | | | | | | | | | | | | | Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump the address length (alen) too, so the address value can be correctly interpreted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
| * i2c: tegra: write clean data to TX FIFOStephen Warren2014-07-03-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra I2C controller's TX FIFO contains 32-bit words. If the final FIFO entry of a transaction contains fewer than 4 bytes, the driver currently fills the unused FIFO bytes with uninitialized data. This can be confusing when reading back the FIFO content for debugging purposes. Solve this by explicitly initializing the variable containing FIFO data before filling it (partially) with data. With this change, send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e. read) branch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
| * i2c: tegra: use repeated start for readsStephen Warren2014-07-03-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I2C read transactions are typically implemented as follows: START(write) address REPEATED_START(read) data... STOP However, Tegra's I2C driver currently implements reads as follows: START(write) address STOP START(read) data... STOP This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board, leading to corrupted read data in some cases. Fix the driver to chain the transactions together using repeated starts to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
* | ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun2014-07-03-0/+5
|/ | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
* i2c: kona: Resolve Kona I2C driver issueSteve Rae2014-06-12-1/+1
| | | | | | - "i2c mw" command hangs (with some compilers) Signed-off-by: Steve Rae <srae@broadcom.com>
* mvtwsi: Remove unnecessary twsi_baud_rate and twsi_slave_address globalsHans de Goede2014-05-14-19/+4
| | | | | | | | | These are used only once, so their is no need to have them global. This also stops mvtwsi from using any bss vars making it easier to use before dram init (to talk to the pmic to set the dram voltage). Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* mvtwsi: Fix clock programmingHans de Goede2014-05-14-5/+2
| | | | | | | | | | | | | | | | The TWSI_FREQUENCY macro was wrong in 2 ways: 1) It was casting the result of the calculations to an u8, while i2c clk rates are often >= 100Khz which won't fit in a u8, drop the cast. 2) It had an extra factor of 2 in the divider which neither the datasheet nor the Linux driver have. The comment for the default value was wrongly saying that m lives in bits 4-7, while in reality it is in bits 3-6, as can be seen from the correct shift by 3 used in i2c_init(). While at it remove the unused twsi_actual_speed variable. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-05-09-168/+314
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| * Merge branch 'u-boot/master'Albert ARIBAUD2014-05-09-17/+42
| |\ | | | | | | | | | | | | | | | | | | Conflicts: drivers/net/Makefile (trivial merge)
| * \ Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-04-21-168/+314
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| | * | i2c, davinci: convert driver to new mutlibus/mutliadapter frameworkVitaly Andrianov2014-04-17-180/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add davinci driver to new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
| | * | i2c, davinci: move i2c_defs.h to the drivers/i2c directoryKaricheri, Muralidharan2014-04-17-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the davinci i2c_defs.h file to drivers.i2c directory. It will allow to reuse the davinci_i2c driver for TI Keystone2 SOCs. Not used "git mv" command to move the file because small part of it with definitions specific for Davinci SOCs has to remain in the arch/arm/include/asm/arch-davinci. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Tom Rini <trini@ti.com>
* | | | i2c: zynq: Fixed compilation errors when using DEBUGJesper B. Christensen2014-05-08-2/+2
| |_|/ |/| | | | | | | | | | | Signed-off-by: Jesper B. Christensen <jesper.christensen@cobham.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | drivers/i2c/fsl_i2c: modify i2c_read to handle multi-byte writeShaveta Leekha2014-04-29-7/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the I2C slaves support accesses in the typical style that is : read/write series of bytes at particular address offset. These transactions look like:" (1) START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP" However there are certain devices which support accesses in terms of the transactions as follows: (2) "START:Address:Tx:Txdata[0..n1]:Clock_stretching: RESTART:Address:Rx:data[0..n2]" Here Txdata is typically a command and some associated data, similarly Rxdata could be command status plus some data received as a response to the command sent. Type (1) transactions are currently supportd in the i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs, RTC, etc fall in this category. To handle type (2) along with type (1) transactions, i2c_read() function has been modified. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
* | | driver/mxc_i2c: Move static data structure to global_dataYork Sun2014-04-29-10/+8
|/ / | | | | | | | | | | | | | | | | This driver needs a data structure in SRAM before SDRAM is available. This is not alway the case using .data section. Moving this data structure to global_data guarantees it is writable. Signed-off-by: York Sun <yorksun@freescale.com> CC: Troy Kisky <troy.kisky@boundarydevices.com>
* | i2c: sh_i2c: bugfix: i2c probe command does not workTetsuyuki Kobayashi2014-04-14-1/+3
|/ | | | | | | | | | | | | | | | | | | | This is regression of commit 2035d77d i2c: sh_i2c: Update to new CONFIG_SYS_I2C framework Before commit 2035d77d, i2c probe command works properly on kzm9g board. KZM-A9-GT# i2c probe Valid chip addresses: 0C 12 1D 32 39 3D 40 60 After commit 2035d77d, i2c probe command does not work. KZM-A9-GT# i2c probe Valid chip addresses: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F sh_i2c_probe() calls sh_i2c_read(), but read length is 0. So acutally it does not read device at all. This patch prepares dummy buffer and read data into it. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* drivers: i2c: delete an unused source fileMasahiro Yamada2014-03-31-387/+0
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-02-26-0/+731
|\ | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/armv7/config.mk board/ti/am43xx/mux.c include/configs/am43xx_evm.h Signed-off-by: Tom Rini <trini@ti.com>
| * i2c: kona: Add Kona I2C driverDarwin Rambo2014-02-22-0/+731
| | | | | | | | | | | | | | | | Add support for the Kona I2C controller found on Broadcom mobile SoCs. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Tim Kryger <tkryger@linaro.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-02-20-3/+0
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| * ARM: IXP: Remove the IXP architecture supportMarek Vasut2014-02-06-3/+0
| | | | | | | | | | | | | | | | | | The architecture is unmaintained and dead, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
* | designware_i2c: remove inclusion of <asm/arch/hardware.h>Alexey Brodkin2014-02-20-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As soon as all boards have their CONFIG_SYS_I2C_BASE defined in configuration files instead of "asm/arch/hardware.h" it's safe to remove the inclusion in question and make driver platform-independent. Cc: Tom Rini <trini@ti.com> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Armando Visconti <armando.visconti@st.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | OMAP24xx I2C: Add support for set-speedHannes Petermaier2014-02-20-50/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for set-speed on the OMAP24xx I2C Adapter. Changes to omap24_i2c_write(...) for polling ARDY Bit from IRQ-Status. Otherwise on a subsequent call the transfer of last byte from the predecessor is aborted and therefore lost. For exmaple when i2c_write(...) is followed by a i2c_setspeed(...) (which has to deactivate and activate master for changing psc,...). Minor cosmetical changes. Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at> Cc: Heiko Schocher <hs@denx.de>
* | i2c: i2c-mxs: Wait for I2C to empty queueMarek Vasut2014-02-20-7/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure the I2C write queue is empty before leaving the mxs_i2c_write(). If we start and I2C write and only wait for ACK, the MXS I2C IP block may enter next operation while still processing the write aftermath internally. This will in turn disrupt one or more subsequent transfer(s). A testcase for this issue is as such. This testcase is also interesting because the first I2C_WRITE which becomes disruptive happens in the 'i2c read' command. The 'i2c read' command first uses I2C_WRITE to send I2C address of the chip and then uses I2C_READ to read data from the chip. After this command completes, the 'i2c probe' will use sequence of I2C_WRITE commands to probe the I2C bus. The problem is that the first I2C_WRITE disrupted the I2C IP block operation and this sideeffect propagates all the way to this next I2C_WRITE used by the 'i2c probe' call. The result is the 'i2c probe' receives an ACK on I2C address 0x00, even if this ACK was owned by the previous I2C_WRITE operation. Note that the 'i2c read' command must read from a valid I2C chip address. Wrong: > i2c probe Valid chip addresses: 50 51 > i2c read 0x50 0x0.2 0x10 0x42000000 > i2c probe Valid chip addresses: 00 50 51 With this patch > i2c probe Valid chip addresses: 50 51 > i2c read 0x50 0x0.2 0x10 0x42000000 > i2c probe Valid chip addresses: 50 51 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
* | designware_i2c: Enhance DesignWare I2C driver address supportChin Liang See2014-02-20-32/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enhance the DesignWare I2C driver to support address length more than 1 byte. This enhancement is required as some I2C slave device such as EEPROM chip might have 16 bit address byte. Signed-off-by: Chin Liang See <clsee@altera.com> Acked-by: Alexey Brodkin <Alexey.Brodkin@synopsys.com> Cc: Tom Rini <trini@ti.com> cc: Armando Visconti <armando.visconti@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de>
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