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path: root/drivers/gpio
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* gpio: s5p: call: dev_get_addr() instead of fdtdec_get_addr()Przemyslaw Marczak2015-10-03-7/+11
| | | | | | | | | | | | | | | | | | | | | | After rework in lib/fdtdec.c, the function fdtdec_get_addr() doesn't work for nodes with #size-cells property set to 0. To get GPIO's 'reg' property, the code should use one of: fdtdec_get_addr_size_auto_no/parent() function. Fortunately dm core provides a function to get the property. This commit reworks function gpio_exynos_bind(), to properly use dev_get_addr() for GPIO device. This prevents setting a wrong base register for Exynos GPIOs. Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon). Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* gpio: tegra: use named constantsStephen Warren2015-10-02-14/+19
| | | | | | | | | | | | | | In order to make it clear what the parameters to set_config() and set_direction() mean, and similarly for the return values from the respective get_*(), define named constants for these values. Disassembly shows no diff in the generated code, except that the order of the code in the branches of tegra_gpio_get_function() gets modified without affecting behaviour. Suggested-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* gpio: tegra: remove unused typeStephen Warren2015-10-02-7/+0
| | | | | | | | These enum values aren't used anywhere. Remove them. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: don't enable GPIOs until direction is setStephen Warren2015-10-02-12/+6
| | | | | | | | | | | | | | | | | | | | | | Tegra's GPIO driver currently enables pins as GPIO as soon as they're requested. This is not safe, since the desired direction and output value are not yet known. This could cause a glitch on the output pins between gpio_request() and gpio_direction_*(), depending on what values happen to be in the GPIO controller's in/out and out-value registers vs. the final desired configuration. To solve this, defer enabling pins as GPIOs until some gpio_direction_*() is invoked, and the desired configuration is explicitly programmed. In theory this change could cause regressions, if code exists that claims a GPIO, never explicitly sets a direction, and then gets/sets the GPIO value based on that assumption. However, I've read through all the Tegra- related board files and device drivers that touch GPIOs and I do not see such buggy code anywhere. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: fix GPIO init table programmingStephen Warren2015-10-02-3/+5
| | | | | | | | | | | | | Tegra's gpio_config_table() currently uses common GPIO APIs. These used to work without requesting the GPIO, but since commit 2fccd2d96bad "tegra: Convert tegra GPIO driver to use driver model" no longer do so. This prevents any of the GPIO initialization table from being applied to HW. Fix gpio_config_table() to directly program the HW to solve this. Fixes: 2fccd2d96bad ("tegra: Convert tegra GPIO driver to use driver model") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-09-13-1/+2
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| * gpio: sh-pfc: fix gpio input readVladimir Barinov2015-08-31-1/+2
| | | | | | | | | | | | | | | | Fix gpio_read: gpio input (INDT) and gpio output (OUTDT) registers have different offset. gpio_read must be performed from INDT. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | gpio: lpc32xx: fix issues with port3 gpioSylvain Lemieux2015-09-11-6/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current simplify lpc32xx gpio driver implementation assume a maximum of 32 GPIO per port; there are a total of 22 GPI, 24 GPO and 6 GPIO to managed on port 3. Update the driver to fix the following: 1) When requesting GPI_xx and GPO_xx on port 3 (xx is the same number) the second call to "gpio_request" will return -EBUSY. 2) The status of GPO_xx pin report the status of the corresponding GPI_xx pin when using the "gpio status" command. 3) The gpio driver may setup the direction register for the wrong gpio when calling "gpio_direction_input" (GPI_xx) or "gpio_direction_output" (GPO_xx) on port 3; the call to the direction is require to use the "gpio status" command. The following change were done in the driver: 1) port3 GPI are cache in a separate 32 bits in the array. 2) port3 direction register written only for GPIO pins. 3) port3 GPO & GPIO (as output) are read using "p3_outp_state". 4) LPC32XX_GPI_P3_GRP updated to match the change. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2015-09-03-0/+133
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| * | rockchip: gpio: Add rockchip GPIO driverSimon Glass2015-09-02-0/+133
| | | | | | | | | | | | | | | | | | | | | This supports RK3288 at present. It does not implement functions or support for pull up/down. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | imx: mxc_gpio: add support for imx7d SoCAdrian Alonso2015-09-02-3/+5
|/ / | | | | | | | | | | | | | | * Add mxc_gpio support for imx7d SoC * Use CONFIG_MX7 to extend mxc gpio driver support for imx7d Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | dm: Use dev_get_addr() where possibleSimon Glass2015-08-31-6/+3
|/ | | | | | | | | | This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
* x86: gpio: Tidy up gpio_ich6_get_base() and callersSimon Glass2015-08-26-3/+3
| | | | | | | | | | | | | This function can return an error. Correct the detection of this error so that it works even with large 32-bit addresses. The return value is set up for returning an I/O address but the function is also used to return a memory-mapped address. Adjust the return code to make this work. Also add a bit more debugging. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: gpio: Correct calls to _ich6_gpio_set_direction()Simon Glass2015-08-26-2/+2
| | | | | | | These calls seem to be incorrect. The function expects an I/O address but the existing callers pass the value at an I/O address. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* gpio: Add DW APB GPIO driverMarek Vasut2015-08-23-0/+175
| | | | | | | | Add driver for the DesignWare APB GPIO IP block. This driver is DM capable and probes from DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
* of: clean up OF_CONTROL ifdef conditionalsMasahiro Yamada2015-08-18-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* sunxi: gpio: Add support for the gpio banks which are part of the R-io clusterHans de Goede2015-08-14-4/+18
| | | | | | | | | | | | | sun6i and later have a couple of io-blocks which are shared between the main CPU core and the "R" cpu which is small embedded cpu which can be active while the main system is suspended. These gpio banks sit at a different mmio address then the normal banks, and have a separate devicetree node and compatible, this adds support for these banks to the sunxi-gpio code when built with device-model support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* gpio: omap: Drop 'method' parameterTom Rini2015-08-12-48/+59
| | | | | | | | | | The "method" parameter was part of the original port of the driver from the kernel. At some point this may have been added to allow for future differentiation (as omap1 and omap2 have different GPIO IP blocks, so this wasn't an unreasonable thing to do). At this point however it's just extra overhead, so drop. Signed-off-by: Tom Rini <trini@konsulko.com>
* dm: gpio: hi6220: Add a hi6220 GPIO driver model driver.Peter Griffin2015-08-12-0/+97
| | | | | | | This patch adds support for the GPIO perif found on hi6220 SoC. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
* drivers: hierarchize drivers Kconfig menuMasahiro Yamada2015-08-12-0/+8
| | | | | | | | | | | The menuconfig for drivers are getting more and more cluttered and unreadable because too many entries are displayed in a single flat menu. Use hierarchic menu for each category. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Update to apply again in a few places, drop USB hunk] Signed-off-by: Tom Rini <trini@konsulko.com>
* dm: gpio: Check a GPIO is valid before using itSimon Glass2015-08-05-1/+5
| | | | | | | | | Since a gpio_desc is allowed to be invalid we should return an error indicating that the operation cannot be completed. This can happen if the GPIO is optional - e.g. some devices may have a reset line and some may not. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add some missing global_data declarations in files that use gdSimon Glass2015-08-05-0/+2
| | | | | | | Some files use global_data but don't declare it. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-08-02-0/+4
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| * mxc: gpio add i.MX6UL supportPeng Fan2015-08-02-0/+4
| | | | | | | | | | | | i.MX6UL does not have GPIO6/7, so do not include them for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | dm: gpio: Add dm_gpio_request() to manually request a GPIOSimon Glass2015-07-21-1/+1
| | | | | | | | | | | | | | This function can be used for testing to manually request a GPIO for use, without resorting to the legacy GPIO API. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: gpio: Add dm_gpio_lookup_name() to look up a GPIO nameSimon Glass2015-07-21-8/+26
| | | | | | | | | | | | | | Provide a driver-model function to look up a GPIO name. Make the standard function use it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: gpio: Allow GPIO uclass to be used in SPLSimon Glass2015-07-21-4/+0
|/ | | | | | | Now that we support driver model in SPL, allow GPIO drivers to be used there also. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-07-07-28/+408
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| * Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-06-08-0/+178
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| | * dm: gpio: vf610: Add GPIO driver supportBhuvanchandra DV2015-06-08-0/+177
| | | | | | | | | | | | | | | | | | Add GPIO driver support to Freescale VF610 Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| | * dm: gpio: uclass: Add flag to control sequence numberingBhuvanchandra DV2015-06-08-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like SPI and I2C few GPIO controllers also have multiple chip instances. This patch adds the flag 'DM_UC_FLAG_SEQ_ALIAS' in gpio_uclass driver to control device sequence numbering. By defalut the dev->r_seq for gpio_uclass will alwalys returns -1, which leads the gpio driver probe failure when using the driver with device trees. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| * | Merge git://git.denx.de/u-boot-sunxiTom Rini2015-06-06-0/+1
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| | * | sunxi: gpio: Add "allwinner,sun8i-a33-pinctrl"Hans de Goede2015-06-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "allwinner,sun8i-a33-pinctrl", this is used by the latest upstream linux sunxi dts files. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | x86: gpio: add pinctrl support from the device treeGabriel Huau2015-06-04-28/+229
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org>
* | | gpio: lpc32xx: Use priv_data instead of platdataAxel Lin2015-07-07-20/+19
|/ / | | | | | | | | | | | | | | | | The LPC32XX GPIO driver platdata currently contains GPIO state information, which should go into priv_data. Thus rename lpc32xx_gpio_platdata to lpc32xx_gpio_priv and convert to use dev_get_priv() instead. Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
* | gpio: stm32: add stm32f1 supportMatt Porter2015-05-28-1/+109
|/ | | | | | Add support for the STM32F1 family to the STM32 gpio driver. Signed-off-by: Matt Porter <mporter@konsulko.com>
* Merge git://git.denx.de/u-boot-samsungTom Rini2015-05-18-33/+42
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| * gpio: s3c: Fix the GPIO driverMarek Vasut2015-05-06-33/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPIO driver didn't correctly compute the bank offset from the GPIO number and caused random writes into the GPIO block address space. Fix the driver so it actually does the writes correctly. While at it, make use of the clrsetbits_le32() mechanisms. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | dm: gpio: Add error handling and a function to claim vector GPIOsSimon Glass2015-05-13-3/+35
| | | | | | | | | | | | | | | | | | gpio_get_values_as_int() should return an error if something goes wrong. Also provide gpio_claim_vector(), a function to request the GPIOs and set them to input mode. Otherwise callers have to do this themselves. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | gpio: stm32_gpio: Use clrsetbits_le32() at appropriate placesAxel Lin2015-05-08-13/+5
|/ | | | | | Use clrsetbits_le32() to replace clrbits_le32() + setbits_le32(). Signed-off-by: Axel Lin <axel.lin@ingics.com>
* sunxi: axp: Remove non driver-model support from the axp gpio codeHans de Goede2015-05-04-41/+8
| | | | | | | | | | | | | | Now that all sunxi boards are using driver-model for gpio (*), we can remove the non driver-model support from the axp gpio code, and the glue to call into the axp gpio code from the sunxi_gpio non driver-model code. *) For the regular u-boot build, SPL still uses non driver-model gpio for now, but the SPL never uses axp gpios support and we were already not building axp-gpio support for the SPL. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: axp: Add driver-model support to the axp_gpio codeHans de Goede2015-05-04-1/+53
| | | | | | | | | | Add driver-model support to the axp_gpio code, note that this needs a small tweak to the driver-model version of sunxi_name_to_gpio to deal with the vbus detect and enable pins which are not standard numbered gpios. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: axp: Move axp gpio code to a separate axpi-gpio driverHans de Goede2015-05-04-11/+154
| | | | | | | | | | | | | | | | | | | | Move the axp-gpio code out of the drivers/power/axp*.c code, and into a new separate axpi-gpio driver. This change drops supports for the gpio3 pin on the axp209, as that requires special handling, and no boards are using it. Besides cleaning things up by moving the code to a separate driver, as a bonus this change also adds support for the (non vusb) gpio pins on the axp221 and the gpio pins on the axp152. The new axp-gpio driver gets its own Kconfig option, and is only enabled on boards which need it. Besides that it only gets enabled in the regular u-boot build and not for the SPL as we never need it in the SPL. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: axp: Change axp_gpio_foo prototypes to match gpio uclass opsHans de Goede2015-05-04-4/+4
| | | | | | | | | | | | | Change the axp_gpio_foo function prototypes to match the gpio uclass op prototypes, this is a preparation patch for moving the axp gpio code to a separate driver-model gpio driver. Note that the ugly calls with a NULL udev pointer in drivers/gpio/sunxi_gpio.c this adds are removed in a later patch. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: gpio: Build sunxi_name_to_gpio_bank for driver-model code tooHans de Goede2015-05-04-14/+14
| | | | | | | | | | When doing a driver-model enabled build we still need sunxi_name_to_gpio_bank (for now) for the mmc pinmux code in board/sunxi/board.c, so build it for driver-model enabled builds too. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: gpio: Add compatible strings for all supported SoCsHans de Goede2015-05-04-0/+7
| | | | | | | | | We want to use driver-model/fdt with other model SoCs too, so add compatible strings for the other SoCs to the dm sunxi gpio code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: gpio: Add temporary implementation of name_to_gpio()Simon Glass2015-05-04-0/+11
| | | | | | | | | | | | Until sunxi moves to device tree (e.g. for USB) we need to convert named GPIOs to numbers. Add a function to do this. This fixes the USB / EHCI support not working on the LinkSprite pcDuino3 (which uses devicemodel). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: gpio: Rename GPIOs to include a 'P' prefixSimon Glass2015-05-04-3/+4
| | | | | | | | | By convention, sunxi GPIOs are named PA1, PA2 instead of A1, A2. Change the driver model GPIO driver for sunxi to use these names. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* gpio: add Xilinx Zynq PS GPIO driverAndrea Scian2015-04-29-0/+221
| | | | | | | | | Most of the code is taken (and adapted) from Linux kernel driver. Just add CONFIG_ZYNQ_GPIO to you config to enable it Signed-off-by: Andrea Scian <andrea.scian@dave.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* mvgpio: remove CONFIG_SHEEVA_88SV331xV5 dependencyZhou Zhu2015-04-23-5/+1
| | | | | | | The Marvell GPIO driver can be used on Marvell platforms other than Sheeva, so remove the ifdef to enable it for others. Signed-off-by: Rob Herring <robh@kernel.org>
generated by cgit v1.1 at 2024-11-05 10:58:43 +0000