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* | gpio: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-5/+3
|/ | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-03-25-0/+127
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| * gpio: Add DM GPIO driver for Marvell MVEBUStefan Roese2016-03-24-0/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a DM GPIO driver for the Marvell MVEBU SoCs. There are other non-DM drivers that might be used on these platforms. But this patch creates a new DM driver. Which will be used by all Armada XP/38x boards. Other MVEBU SoC (Kirkwood / Orion) may follow once they support DM as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | sunxi: Add a bunch of missing compatible strings to sunxi_gpio.cHans de Goede2016-03-23-1/+14
|/ | | | | | | | | | | The kernel has different compatible strings for the pio block because the pin-muxing is different on all the different SoCs, but sunxi_gpio.c only support the basic gpio functionality, which is identical everywhere. Add the missing compatible strings for various SoC models. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* x86: broadwell: Add a GPIO driverSimon Glass2016-03-17-0/+208
| | | | | | | Add a GPIO driver for the GPIO peripheral found on broadwell devices. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop all the old pin configuration codeSimon Glass2016-03-17-11/+0
| | | | | | | | We don't need this anymore - we can use device tree and the new pinconfig driver instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: gpio: Allow the pinctrl driver to set up the pin configSimon Glass2016-03-17-175/+5
| | | | | | | | Rather than setting up the pin configuration in the GPIO driver, use the new pinctrl driver to do it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: gpio: Correct GPIO setup orderingSimon Glass2016-03-17-1/+3
| | | | | | | | | | | | | The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO is probed. However, it assumes that the first GPIO to be probed is in the first GPIO bank. If this is not the case then the init will write to the wrong registers. Fix this. Also add a note that this code is deprecated. We should move to using device tree instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* gpio: Use const where possibleSimon Glass2016-03-17-5/+5
| | | | | | | | Some functions do not change the struct gpio_desc parameter. Update these to use const so this is clear. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* gpio: Add a function to obtain a GPIO vector valueSimon Glass2016-03-17-0/+18
| | | | | | | | | | We can use GPIOs as binary digits for reading 'strapping' values. Each GPIO is assigned a single bit and can be set high or low on the circuit board. We already have a legacy function for reading these values. Add one that supports driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: Use uclass_first_device_err() where it is usefulSimon Glass2016-03-14-3/+1
| | | | | | Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* gpio: uniphier: add driver for UniPhier GPIO controllerMasahiro Yamada2016-02-29-0/+154
| | | | | | | This GPIO controller device is used on UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* stm32: add support for stm32f7 & stm32f746 discovery boardVikas Manocha2016-02-24-3/+3
| | | | | | This patch adds support for stm32f7 family & stm32f746 board. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* gpio: stm32_gpio: move base addresses to the soc fileVikas Manocha2016-02-24-18/+0
| | | | | | | Base addresses for GPIOs could be different for different socs, this patch moves the base addresses from driver to the soc specific location. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* gpio: stm32_gpio: move clock config from driver to boardVikas Manocha2016-02-24-5/+0
| | | | | | | This patch removes the gpio clock enable from gpio driver & move it in the board code, making it possible to use the gpio driver with other socs. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* tegra: gpio: Show the GPIO value for outputsSimon Glass2016-02-16-1/+4
| | | | | | | | | | | | | | | | | | | The tegra GPIO controller has two ways of reading the value of a GPIO. It can supply the 'input' value (which is the value read from the pin) and the 'output' value (which is the value being driven from the pin. With a GPIO set to output mode, the 'input' value is always low which is not very useful. This has the unfortunate result that setting a GPIO high still leaves it showing as low in the 'gpio status' command. Adjust the driver to check which direction the GPIO is set to, then read the value from the appropriate register: 'input' for input GPIOs, 'output' for output GPIOs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingTom Rini2016-02-08-2/+2
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| * Use correct spelling of "U-Boot"Bin Meng2016-02-06-2/+2
| | | | | | | | | | | | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* | x86: ich6_gpio: Convert to use proper DM APIBin Meng2016-02-05-102/+23
|/ | | | | | | | | | | | | | | | At present this GPIO driver still uses the legacy PCI API. Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has nodes for the GPIO peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the PCH device. Update the device tree files to show the GPIO controller within the PCH, so that PCI access works as expected. This also adds '#address-cells' and '#size-cells' to the PCH node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* dm: vybrid_gpio: Drop legacy codeBhuvanchandra DV2016-02-02-18/+0
| | | | | | | | All boards using this driver are with device tree support, hence drop the legacy code in driver to have a pure DT solution. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* drivers: gpio: add driver for Microchip PIC32 GPIO controller.Purna Chandra Mandal2016-02-01-1/+182
| | | | | | | | | | | | In PIC32 GPIO controller is part of PIC32 pin controller. PIC32 has ten independently programmable ports and each with multiple pins. Each of these pins can be configured and used as GPIO, provided they are not in use for other peripherals. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* bug.h: move BUILD_BUG_* defines to include/linux/bug.hMasahiro Yamada2016-01-25-0/+1
| | | | | | | | | | | | | | | | BUILD_BUG_* macros have been defined in several headers. It would be nice to collect them in include/linux/bug.h like Linux. This commit is cherry-picking useful macros from include/linux/bug.h of Linux 4.4. I did not import BUILD_BUG_ON_MSG() because it would not work if it is used with include/common.h in U-Boot. I'd like to postpone it until the root cause (the "error()" macro in include/common.h causes the name conflict with "__attribute__((error()))") is fixed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* rockchip: gpio: Implement the get_function() methodSimon Glass2016-01-21-4/+36
| | | | | | | Provide this method so that 'gpio status' works fully. It now shows whether a pin is used for input, output or some other function. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: gpio: Read the GPIO value correctlySimon Glass2016-01-21-1/+1
| | | | | | This function should return 0 or 1, not a mask. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: gpio: Allow the uclass to work without printf()Simon Glass2016-01-20-0/+8
| | | | | | | For SPL we don't really need sprintf() and with tiny-printf this is not available. Allow this to be dropped in SPL when using tiny-printf. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add more SPDX-License-Identifier tagsTom Rini2016-01-19-13/+1
| | | | | | | | | In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
* gpio: mxs: add name_to_gpio() functionMåns Rullgård2016-01-07-0/+15
| | | | | | | | | | | | Override the default name_to_gpio() function with one that accepts strings of the form bank:pin. If a colon is present in the provided name, it behaves like the default version. This lets the "gpio" command work with sane names rather than requiring the user to enter the bank/pin composite in decimal. Signed-off-by: Mans Rullgard <mans@mansr.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* Change e-mail address of Kamil LulkoKamil Lulko2015-12-05-1/+1
| | | | Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
* gpio: atmel: Add the PIO4 driver supportWenyou Yang2015-11-30-0/+308
| | | | | | | The PIO4 is introduced from SAMA5D2, as a new version for Atmel PIO controller. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* altera_pio: change ioremap to map_physmemThomas Chou2015-11-18-2/+3
| | | | | | | Change ioremap() to map_physmem(), as it is more used in u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* i2c: Fix pca953x endianess issueDirk Eibach2015-11-12-1/+3
| | | | | | | By reading 2 consecutive bytes from i2c to an u16 value we have an endianess issue. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* nios2 : convert altera_pio to driver modelThomas Chou2015-10-23-240/+83
| | | | | | | | Convert altera_pio to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: gpio: omap: add support for parsing additional gpio parametersMugunthan V N2015-10-22-0/+11
| | | | | | | | | | | | | With DM_GPIO, gpio parameters like ACTIVE_(LOW/HIGH) are to be parsed in xlate gpio drivers-ops. Since xlate is not implemented in omap_gpio driver, the driver considers all gpio to be ACTIVE_HIGH which is the default case and fails to return actual gpio status for ACTIVE_LOW gpios. So adding .xlate ops to omap_gpio. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sunxi: power: Unify axp pmic function namesHans de Goede2015-10-20-10/+1
| | | | | | | | | Stop prefixing the axp functions for setting voltages, etc. with the model number, there ever is only one pmic driver built into u-boot, this allows simplifying the callers. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* gpio: s5p: call: dev_get_addr() instead of fdtdec_get_addr()Przemyslaw Marczak2015-10-03-7/+11
| | | | | | | | | | | | | | | | | | | | | | After rework in lib/fdtdec.c, the function fdtdec_get_addr() doesn't work for nodes with #size-cells property set to 0. To get GPIO's 'reg' property, the code should use one of: fdtdec_get_addr_size_auto_no/parent() function. Fortunately dm core provides a function to get the property. This commit reworks function gpio_exynos_bind(), to properly use dev_get_addr() for GPIO device. This prevents setting a wrong base register for Exynos GPIOs. Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon). Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* gpio: tegra: use named constantsStephen Warren2015-10-02-14/+19
| | | | | | | | | | | | | | In order to make it clear what the parameters to set_config() and set_direction() mean, and similarly for the return values from the respective get_*(), define named constants for these values. Disassembly shows no diff in the generated code, except that the order of the code in the branches of tegra_gpio_get_function() gets modified without affecting behaviour. Suggested-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* gpio: tegra: remove unused typeStephen Warren2015-10-02-7/+0
| | | | | | | | These enum values aren't used anywhere. Remove them. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: don't enable GPIOs until direction is setStephen Warren2015-10-02-12/+6
| | | | | | | | | | | | | | | | | | | | | | Tegra's GPIO driver currently enables pins as GPIO as soon as they're requested. This is not safe, since the desired direction and output value are not yet known. This could cause a glitch on the output pins between gpio_request() and gpio_direction_*(), depending on what values happen to be in the GPIO controller's in/out and out-value registers vs. the final desired configuration. To solve this, defer enabling pins as GPIOs until some gpio_direction_*() is invoked, and the desired configuration is explicitly programmed. In theory this change could cause regressions, if code exists that claims a GPIO, never explicitly sets a direction, and then gets/sets the GPIO value based on that assumption. However, I've read through all the Tegra- related board files and device drivers that touch GPIOs and I do not see such buggy code anywhere. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: fix GPIO init table programmingStephen Warren2015-10-02-3/+5
| | | | | | | | | | | | | Tegra's gpio_config_table() currently uses common GPIO APIs. These used to work without requesting the GPIO, but since commit 2fccd2d96bad "tegra: Convert tegra GPIO driver to use driver model" no longer do so. This prevents any of the GPIO initialization table from being applied to HW. Fix gpio_config_table() to directly program the HW to solve this. Fixes: 2fccd2d96bad ("tegra: Convert tegra GPIO driver to use driver model") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-09-13-1/+2
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| * gpio: sh-pfc: fix gpio input readVladimir Barinov2015-08-31-1/+2
| | | | | | | | | | | | | | | | Fix gpio_read: gpio input (INDT) and gpio output (OUTDT) registers have different offset. gpio_read must be performed from INDT. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | gpio: lpc32xx: fix issues with port3 gpioSylvain Lemieux2015-09-11-6/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current simplify lpc32xx gpio driver implementation assume a maximum of 32 GPIO per port; there are a total of 22 GPI, 24 GPO and 6 GPIO to managed on port 3. Update the driver to fix the following: 1) When requesting GPI_xx and GPO_xx on port 3 (xx is the same number) the second call to "gpio_request" will return -EBUSY. 2) The status of GPO_xx pin report the status of the corresponding GPI_xx pin when using the "gpio status" command. 3) The gpio driver may setup the direction register for the wrong gpio when calling "gpio_direction_input" (GPI_xx) or "gpio_direction_output" (GPO_xx) on port 3; the call to the direction is require to use the "gpio status" command. The following change were done in the driver: 1) port3 GPI are cache in a separate 32 bits in the array. 2) port3 direction register written only for GPIO pins. 3) port3 GPO & GPIO (as output) are read using "p3_outp_state". 4) LPC32XX_GPI_P3_GRP updated to match the change. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2015-09-03-0/+133
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| * | rockchip: gpio: Add rockchip GPIO driverSimon Glass2015-09-02-0/+133
| | | | | | | | | | | | | | | | | | | | | This supports RK3288 at present. It does not implement functions or support for pull up/down. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | imx: mxc_gpio: add support for imx7d SoCAdrian Alonso2015-09-02-3/+5
|/ / | | | | | | | | | | | | | | * Add mxc_gpio support for imx7d SoC * Use CONFIG_MX7 to extend mxc gpio driver support for imx7d Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | dm: Use dev_get_addr() where possibleSimon Glass2015-08-31-6/+3
|/ | | | | | | | | | This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
* x86: gpio: Tidy up gpio_ich6_get_base() and callersSimon Glass2015-08-26-3/+3
| | | | | | | | | | | | | This function can return an error. Correct the detection of this error so that it works even with large 32-bit addresses. The return value is set up for returning an I/O address but the function is also used to return a memory-mapped address. Adjust the return code to make this work. Also add a bit more debugging. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: gpio: Correct calls to _ich6_gpio_set_direction()Simon Glass2015-08-26-2/+2
| | | | | | | These calls seem to be incorrect. The function expects an I/O address but the existing callers pass the value at an I/O address. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* gpio: Add DW APB GPIO driverMarek Vasut2015-08-23-0/+175
| | | | | | | | Add driver for the DesignWare APB GPIO IP block. This driver is DM capable and probes from DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
* of: clean up OF_CONTROL ifdef conditionalsMasahiro Yamada2015-08-18-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.1 at 2024-11-07 22:24:19 +0000