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* arm: socfpga: Fix FPGA bitstream programming routineMarek Vasut2015-08-08-0/+3
| | | | | | | | | In case the FPGA bitstream is aligned to 4 bytes, skip the part of the assembler which handles unaligned bitstream. Otherwise, that part will loop indefinitelly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* fpga: xilinx: Show fpga info if definedMichal Simek2015-01-21-4/+5
| | | | | | | Show fpga_op->info even if desc->iface_fns is not defined. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* fpga: xilinx: Check if fpga operations are definedMichal Simek2015-01-21-2/+15
| | | | | | | Ensure that operations are correctly setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* fpga: Export fpga_get_desc for SPLMichal Simek2015-01-21-1/+1
| | | | | | | SPL needs to detect FPGA device which will be used for loading bitstream. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fs: API changes enabling extra parameter to return size of type loff_tSuriyan Ramasami2014-11-23-5/+5
| | | | | | | | | | | | | | | The sandbox/ext4/fat/generic fs commands do not gracefully deal with files greater than 2GB. Negative values are returned in such cases. To handle this, the fs functions have been modified to take an additional parameter of type "* loff_t" which is then populated. The return value of the fs functions are used only for error conditions. Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> [trini: Update board/gdsys/p1022/controlcenterd-id.c, drivers/fpga/zynqpl.c for changes] Signed-off-by: Tom Rini <trini@ti.com>
* arm: socfpga: fpga: Add SoCFPGA FPGA programming interfacePavel Machek2014-10-06-0/+305
| | | | | | | | | | | | | | | | | | | Add code necessary to program the FPGA part of SoCFPGA from U-Boot with an RBF blob. This patch also integrates the code into the FPGA driver framework in U-Boot so it can be used via the 'fpga' command. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move the not-CPU specific stuff into drivers/fpga/ and base this on the cleaned up altera FPGA support.
* fpga: altera: Turn the switches into table lookupMarek Vasut2014-10-06-111/+60
| | | | | | | | | | | | | | | | Add a table of FPGA family with matching functions associated with it and make all the code just look up the family in that table and call the associated function instead of the horrible switch voodoo which was duplicated all over the place. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* fpga: altera: Make altera_validate return normal valuesMarek Vasut2014-10-06-9/+9
| | | | | | | | | | | | | | | Make the function return either 0 or -EINVAL, that is, normal expected error codes and success codes instead of true/false nonsense. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* fpga: altera: Move altera_validate to the topMarek Vasut2014-10-06-32/+26
| | | | | | | | | | | | | | Move the function to the top of the file to avoid forward declaration. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* fpga: altera: More indentation trimdownMarek Vasut2014-10-06-118/+120
| | | | | | | | | | | | | | | Further improve the indentation in the rest of the file, where the indentation is initially a bit less brutal. There is no functional change in this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* fpga: altera: Clean up altera_validate functionMarek Vasut2014-10-06-22/+21
| | | | | | | | | | | | | Boldly go, where no programmer has gone before and just clean up the indentation mayhem. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
* fpga: altera: Clean up the printing and debugMarek Vasut2014-10-06-59/+58
| | | | | | | | | | | | | | Clean up the printf() statements and get rid of the PRINTF() macro by replacing it with debug_cond(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* m68k: Fix warnings with gcc 4.6Simon Glass2014-06-11-6/+6
| | | | | | | | Most of the warnings seem to be related to using 'int' for size_t. Change this and fix up the remaining warnings and problems. For bootm, the warning was masked by others, and there is an actual bug in the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* fpga: Added support to load bit stream from SD/MMCSiva Durga Prasad Paladugu2014-05-20-0/+129
| | | | | | | | | | | | Added support to load a bitstream image in chunks by reading it in chunks from SD/MMC. Command format: loadfs [dev] [address] [image size] [blocksize] <interface> [<dev[:part]>] <filename> Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: zynqpl: Clean partial bitstream handlingMichal Simek2014-05-20-12/+6
| | | | | | | | Do not do partial bitstream detection based on bitstream size and use bitstream_type argument which is passed from the fpga core. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: Define bitstream type based on command selectionMichal Simek2014-05-20-12/+19
| | | | | | | | | | Clean up partial, full and compressed bitstream handling. U-Boot supports full bitstream loading and partial based on detection which is not 100% correct. Extending fpga_load/fpga_loadbitstream() with one more argument which stores bitstream type. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: zynq: Use helper function zynq_validate_bitstreamSiva Durga Prasad Paladugu2014-05-13-7/+25
| | | | | | | | Use helper function zynq_validate_bitstream so that the code can be reused easily for different cases of dma transfer. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: zynq: Use helper functions for zynq dmaSiva Durga Prasad Paladugu2014-05-13-86/+115
| | | | | | | | | | Use zynq_dma_xfer_init, zynq_align_dma_buffer, zynq_dma_transfer helper function performing dma transfers so that the code can be reused easily for different cases of dma transfer. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: zynq: Remove sparse warningsMichal Simek2014-05-13-2/+2
| | | | | | | | Warnings: drivers/fpga/zynqpl.c:150:32: warning: Using plain integer as NULL pointer drivers/fpga/zynqpl.c:152:16: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: xilinx: Simplify load/dump/info function handlingMichal Simek2014-05-13-165/+43
| | | | | | | | Connect FPGA version with appropriate operations to remove huge switch-cases for every FPGA family. Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: xilinx: Avoid CamelCase for in Xilinx_descMichal Simek2014-05-13-47/+47
| | | | | | No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: virtex2: Avoid CamelCaseMichal Simek2014-05-13-24/+24
| | | | | | No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: spartan3: Avoid CamelCaseMichal Simek2014-05-13-27/+27
| | | | | | No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: spartan2: Avoid CamelCaseMichal Simek2014-05-13-27/+27
| | | | | | No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sizes.h - consolidate for all architecturesAlexey Brodkin2014-03-04-1/+1
| | | | | | | | | | | | | | | | Copied from Linux sources "include/linux/sizes.h" commit 413541dd66d51f791a0b169d9b9014e4f56be13c Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Tom Rini <trini@ti.com> Cc: Stefan Roese <sr@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Tom Rini <trini@ti.com> Acked-by: Stefan Roese <sr@denx.de> [trini: Add bcm Kona platforms to the patch] Signed-off-by: Tom Rini <trini@ti.com>
* fpga: zynq: Correct fpga load when buf is not alignedNovasys Ingenierie2014-02-06-0/+10
| | | | | | | | | | | | When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is not aligned, new_buf address became greater then buf_start address and the load_word loop corrupts bit file data. A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data before buf but permits to load correctly. Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* drivers: descend into sub directories only when it is necessaryMasahiro Yamada2013-11-17-2/+0
| | | | | | | - Descend into drivers/fpga/ only when CONFIG_FPGA=y - Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=y Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* fpga: zynqpl: Do not place bitstream below 1MBMichal Simek2013-11-06-0/+7
| | | | | | | DMA doesn't work when src is placed below 1MB limit. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* fpga: zynqpl: Add dcache flush supportJagannadha Sutradharudu Teki2013-11-06-2/+6
| | | | | | | Buffers must be cache and dma aligned. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* drivers: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-33/+11
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* fpga: zynqpl: Clear loopback mode during device initSoren Brinkmann2013-08-12-0/+4
| | | | | | | | | | | | | | | Some versions of the Zynq first stage boot loader enable PCAP loopback during boot regardless of whether or not the boot image includes PL configuration. This behavior only appears in certain boot modes (notably QSPI boot). Attempting to configure the PL with the loopback bit set will result in timeouts and will prevent successful configuration. In order to avoid this problem, and to avoid dependency on the version of the FSBL used to boot the system, ensure that the loopback enable bit is cleared when loading the driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: zynqpl: Add support for zc7100 device.Michal Simek2013-08-12-1/+1
| | | | | | | | | | - Add support for zc7100 device. - FPGA programming on few of the SOC(zc7100) takes more than 1sec, hence increased the program time by 4sec to sync' all soc's. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-231/+13
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* fpga: Check device name against bitstream nameMichal Simek2013-05-06-2/+25
| | | | | | | | Ensure that wrong bitstream won't be loaded to current device. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* fpga: zynq: Add support for loading bitstreamMichal Simek2013-05-06-0/+393
| | | | | | | | | | | | | Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* fpga: Change the first parameter in fpga_loadbitstreamMichal Simek2013-05-06-3/+3
| | | | | | | | | All fpga functions use devnum as int. Only fpga_loadbitstream is using it as unsinged long dev. This patch synchronize it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* cmd: fpga: Move fpga_loadbitstream to fpga.cMichal Simek2013-05-06-0/+95
| | | | | | | | | In bitstream decoding you can directly check device which you want to load and in fpga.c are fpga_validate and fpga_dev_info functions which should be used for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* fpga: Fix debug message compilation errorMichal Simek2013-05-06-1/+1
| | | | | | | | | | | | CONFIG_FPGA in past was a bitfield where bits were use for vendor identification. This fix should be the part of this commit: "Improve configuration of FPGA subsystem" (sha1: 0133502e39ff89b67c26cb4015e0e7e8d9571184) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* fpga: Clean coding styleMichal Simek2013-05-06-118/+98
| | | | | | | No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* Consolidate bool typeYork Sun2013-04-01-92/+92
| | | | | | | | | | | | | 'bool' is defined in random places. This patch consolidates them into a single header file include/linux/types.h, using stdbool.h introduced in C99. All other #define, typedef and enum are removed. They are all consistent with true = 1, false = 0. Replace FALSE, False with false. Replace TRUE, True with true. Skip *.py, *.php, lib/* files. Signed-off-by: York Sun <yorksun@freescale.com>
* FPGA: Cyclon II: Correctly reset the FPGA before configurationStephan Gatzka2012-10-29-0/+2
| | | | | | | | | | | Deassert the CONFIG pin before asserting it again. This assures that the FPGA will be resetted and therefore configuration will be correctly enabled. This is also already done on other FPGA's, e.g. Stratix. Signed-off-by: Stephan Gatzka <stephan.gatzka@hbm.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Remove execute permissions from source filesThomas Weber2012-03-04-0/+0
| | | | Signed-off-by: Thomas Weber <weber@corscience.de>
* fpga: Spartan-3: let print the progress if configuredStefano Babic2012-01-05-1/+0
| | | | | | | | CONFIG_SYS_FPGA_PROG_FEEDBACK was already introduced to print the current status of FPGA loading - an undef in the code made this CONFIG_ useless. Signed-off-by: Stefano Babic <sbabic@denx.de>
* FPGA: drivers/fpga/ivm_core.c: GCC4.6 fix build warningsStefano Babic2011-11-16-2/+0
| | | | | | | | | Fix: ivm_core.c: In function 'ispVMLCOUNT': ivm_core.c:2105:16: warning: unused variable 'usByte' Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Wolfgang Denk <wd@denx.de>
* GCC4.6: Squash warnings in lattice.cMarek Vasut2011-10-27-1/+1
| | | | | | | | | | | | lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument 3 has type 'const char *' lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument 4 has type 'long unsigned int' Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org>
* FPGA: constify Lattice FPGA codeWolfgang Denk2011-09-05-3/+3
| | | | | | | | | | | | | The Lattice code was missed by commit e6a857d "fpga: constify to fix build warning" resulting in such warnings: fpga.c: In function 'fpga_load': fpga.c:238: warning: passing argument 2 of 'lattice_load' discards qualifiers from pointer target type fpga.c: In function 'fpga_dump': fpga.c:278: warning: passing argument 2 of 'lattice_dump' discards qualifiers from pointer target type Signed-off-by: Wolfgang Denk <wd@denx.de> cc: Stefano Babic <sbabic@denx.de>
* fpga: constify to fix build warningWolfgang Denk2011-08-01-55/+55
| | | | | | | | | | | | | | | Fix compiler warning: cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data' from incompatible pointer type Adding the needed 'const' here entails a whole bunch of additonal changes all over the FPGA code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> Cc: Murray Jensen <Murray.Jensen@csiro.au> Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de>
* fpga: support FPP Cyclone configurationMichael Jones2011-07-28-0/+10
| | | | | | Support FPGAs which use Fast Passive Parallel configuration Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
* altera: fix printf typoMichael Jones2011-07-28-1/+1
| | | | | Signed-off-by: Michael Jones <michael.jones@matrix-vision.de> Acked-by: Detlev Zundel <dzu@denx.de>
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