summaryrefslogtreecommitdiff
path: root/drivers/fpga
Commit message (Collapse)AuthorAgeLines
* fpga: zynqpl: Clear loopback mode during device initSoren Brinkmann2013-08-12-0/+4
| | | | | | | | | | | | | | | Some versions of the Zynq first stage boot loader enable PCAP loopback during boot regardless of whether or not the boot image includes PL configuration. This behavior only appears in certain boot modes (notably QSPI boot). Attempting to configure the PL with the loopback bit set will result in timeouts and will prevent successful configuration. In order to avoid this problem, and to avoid dependency on the version of the FSBL used to boot the system, ensure that the loopback enable bit is cleared when loading the driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: zynqpl: Add support for zc7100 device.Michal Simek2013-08-12-1/+1
| | | | | | | | | | - Add support for zc7100 device. - FPGA programming on few of the SOC(zc7100) takes more than 1sec, hence increased the program time by 4sec to sync' all soc's. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-231/+13
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* fpga: Check device name against bitstream nameMichal Simek2013-05-06-2/+25
| | | | | | | | Ensure that wrong bitstream won't be loaded to current device. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* fpga: zynq: Add support for loading bitstreamMichal Simek2013-05-06-0/+393
| | | | | | | | | | | | | Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* fpga: Change the first parameter in fpga_loadbitstreamMichal Simek2013-05-06-3/+3
| | | | | | | | | All fpga functions use devnum as int. Only fpga_loadbitstream is using it as unsinged long dev. This patch synchronize it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* cmd: fpga: Move fpga_loadbitstream to fpga.cMichal Simek2013-05-06-0/+95
| | | | | | | | | In bitstream decoding you can directly check device which you want to load and in fpga.c are fpga_validate and fpga_dev_info functions which should be used for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* fpga: Fix debug message compilation errorMichal Simek2013-05-06-1/+1
| | | | | | | | | | | | CONFIG_FPGA in past was a bitfield where bits were use for vendor identification. This fix should be the part of this commit: "Improve configuration of FPGA subsystem" (sha1: 0133502e39ff89b67c26cb4015e0e7e8d9571184) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* fpga: Clean coding styleMichal Simek2013-05-06-118/+98
| | | | | | | No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* Consolidate bool typeYork Sun2013-04-01-92/+92
| | | | | | | | | | | | | 'bool' is defined in random places. This patch consolidates them into a single header file include/linux/types.h, using stdbool.h introduced in C99. All other #define, typedef and enum are removed. They are all consistent with true = 1, false = 0. Replace FALSE, False with false. Replace TRUE, True with true. Skip *.py, *.php, lib/* files. Signed-off-by: York Sun <yorksun@freescale.com>
* FPGA: Cyclon II: Correctly reset the FPGA before configurationStephan Gatzka2012-10-29-0/+2
| | | | | | | | | | | Deassert the CONFIG pin before asserting it again. This assures that the FPGA will be resetted and therefore configuration will be correctly enabled. This is also already done on other FPGA's, e.g. Stratix. Signed-off-by: Stephan Gatzka <stephan.gatzka@hbm.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Remove execute permissions from source filesThomas Weber2012-03-04-0/+0
| | | | Signed-off-by: Thomas Weber <weber@corscience.de>
* fpga: Spartan-3: let print the progress if configuredStefano Babic2012-01-05-1/+0
| | | | | | | | CONFIG_SYS_FPGA_PROG_FEEDBACK was already introduced to print the current status of FPGA loading - an undef in the code made this CONFIG_ useless. Signed-off-by: Stefano Babic <sbabic@denx.de>
* FPGA: drivers/fpga/ivm_core.c: GCC4.6 fix build warningsStefano Babic2011-11-16-2/+0
| | | | | | | | | Fix: ivm_core.c: In function 'ispVMLCOUNT': ivm_core.c:2105:16: warning: unused variable 'usByte' Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Wolfgang Denk <wd@denx.de>
* GCC4.6: Squash warnings in lattice.cMarek Vasut2011-10-27-1/+1
| | | | | | | | | | | | lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument 3 has type 'const char *' lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument 4 has type 'long unsigned int' Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org>
* FPGA: constify Lattice FPGA codeWolfgang Denk2011-09-05-3/+3
| | | | | | | | | | | | | The Lattice code was missed by commit e6a857d "fpga: constify to fix build warning" resulting in such warnings: fpga.c: In function 'fpga_load': fpga.c:238: warning: passing argument 2 of 'lattice_load' discards qualifiers from pointer target type fpga.c: In function 'fpga_dump': fpga.c:278: warning: passing argument 2 of 'lattice_dump' discards qualifiers from pointer target type Signed-off-by: Wolfgang Denk <wd@denx.de> cc: Stefano Babic <sbabic@denx.de>
* fpga: constify to fix build warningWolfgang Denk2011-08-01-55/+55
| | | | | | | | | | | | | | | Fix compiler warning: cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data' from incompatible pointer type Adding the needed 'const' here entails a whole bunch of additonal changes all over the FPGA code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> Cc: Murray Jensen <Murray.Jensen@csiro.au> Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de>
* fpga: support FPP Cyclone configurationMichael Jones2011-07-28-0/+10
| | | | | | Support FPGAs which use Fast Passive Parallel configuration Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
* altera: fix printf typoMichael Jones2011-07-28-1/+1
| | | | | Signed-off-by: Michael Jones <michael.jones@matrix-vision.de> Acked-by: Detlev Zundel <dzu@denx.de>
* add Xilinx_abort_fn to Xilinx_Spartan3_Slave_Serial_fnsWolfgang Wegner2010-11-30-0/+6
| | | | | | | | Currently the hardware was left in an undefined state in case Spartan3 serial load failed. This patch adds Xilinx_abort_fn to give the board a possibility to clean up in this case. Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
* Switch from archive libraries to partial linkingSebastien Carlier2010-11-17-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, weak symbols were not overridden by non-weak symbols found in archive libraries when linking with recent versions of binutils. As stated in the System V ABI, "the link editor does not extract archive members to resolve undefined weak symbols". This commit changes all Makefiles to use partial linking (ld -r) instead of creating library archives, which forces all symbols to participate in linking, allowing non-weak symbols to override weak symbols as intended. This approach is also used by Linux, from which the gmake function cmd_link_o_target (defined in config.mk and used in all Makefiles) is inspired. The name of each former library archive is preserved except for extensions which change from ".a" to ".o". This commit updates references accordingly where needed, in particular in some linker scripts. This commit reveals board configurations that exclude some features but include source files that depend these disabled features in the build, resulting in undefined symbols. Known such cases include: - disabling CMD_NET but not CMD_NFS; - enabling CONFIG_OF_LIBFDT but not CONFIG_QE. Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
* Coding Style cleanupWolfgang Denk2010-10-27-2/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* FPGA: fix support for non-Lattice devicesWolfgang Denk2010-10-18-0/+12
| | | | | | | | | | | | | | | | | | | | | Commit 3b8ac464 "FPGA: add support for downloading Lattice bitstream" added support for Lattice devices, but failed to add #ifdef's that are needed when building for non-Lattice devices, which results in build failures like these: Configuring for GEN860T board... drivers/fpga/libfpga.a(fpga.o): In function `fpga_dev_info': /home/wd/git/u-boot/work/drivers/fpga/fpga.c:145: undefined reference to `lattice_info' drivers/fpga/libfpga.a(fpga.o): In function `fpga_dump': /home/wd/git/u-boot/work/drivers/fpga/fpga.c:269: undefined reference to `lattice_dump' drivers/fpga/libfpga.a(fpga.o): In function `fpga_load': /home/wd/git/u-boot/work/drivers/fpga/fpga.c:233: undefined reference to `lattice_load' make: *** [u-boot] Error 1 Add the missing code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* FPGA: add support for downloading Lattice bitstreamStefano Babic2010-10-13-0/+3578
| | | | | | | | | | | | | | The patch adds support to load a Lattice's bitstream image (called VME file) into a Lattice FPGA. The code containing the state machine delivered as part of Lattice's ispVMtools is integrated. The FPGA is programmed using the JTAG interface. The board maintainer must provide accessors to drive the JTAG signals TCK, TMS, TDI and to get the value of the input signal TDO. Signed-off-by: Stefano Babic <sbabic@denx.de>
* add block write function to spartan3 slave serial loadWolfgang Wegner2010-03-24-25/+29
| | | | | | | | | | | Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
* fpga: Remove relocation fixupsPeter Tyser2009-10-03-830/+5
| | | | | | | | PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* fpga: Fix Spartan III FPGA bootingMatthias Fuchs2009-02-21-15/+7
| | | | | | | | | | | | This patch does some minor fixing of the Xilinx Spartan III FPGA boot code: - Fixed call order of post configuration callback and success message printing (result of copy-paste?) - remove obsolete comment - minor coding style cleanup Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* fpga: Fix Spartan II FPGA bootingMatthias Fuchs2009-02-21-21/+11
| | | | | | | | | | | | | | This patch does some minor fixing of the Xilinx Spartan II FPGA boot code: - Fixed call order of post configuration callback and success message printing (result of copy-paste?) - relocate post configuration callback only when it is implemented - remove obsolete comment - minor coding style cleanup Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* FPGA: move fpga drivers to drivers/fpgaJean-Christophe PLAGNIOL-VILLARD2008-12-05-0/+3762
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
generated by cgit v1.1 at 2024-12-23 17:19:48 +0000