summaryrefslogtreecommitdiff
path: root/drivers/fpga/zynqpl.c
Commit message (Collapse)AuthorAgeLines
* sizes.h - consolidate for all architecturesAlexey Brodkin2014-03-04-1/+1
| | | | | | | | | | | | | | | | Copied from Linux sources "include/linux/sizes.h" commit 413541dd66d51f791a0b169d9b9014e4f56be13c Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Tom Rini <trini@ti.com> Cc: Stefan Roese <sr@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Tom Rini <trini@ti.com> Acked-by: Stefan Roese <sr@denx.de> [trini: Add bcm Kona platforms to the patch] Signed-off-by: Tom Rini <trini@ti.com>
* fpga: zynq: Correct fpga load when buf is not alignedNovasys Ingenierie2014-02-06-0/+10
| | | | | | | | | | | | When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is not aligned, new_buf address became greater then buf_start address and the load_word loop corrupts bit file data. A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data before buf but permits to load correctly. Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: zynqpl: Do not place bitstream below 1MBMichal Simek2013-11-06-0/+7
| | | | | | | DMA doesn't work when src is placed below 1MB limit. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* fpga: zynqpl: Add dcache flush supportJagannadha Sutradharudu Teki2013-11-06-2/+6
| | | | | | | Buffers must be cache and dma aligned. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* fpga: zynqpl: Clear loopback mode during device initSoren Brinkmann2013-08-12-0/+4
| | | | | | | | | | | | | | | Some versions of the Zynq first stage boot loader enable PCAP loopback during boot regardless of whether or not the boot image includes PL configuration. This behavior only appears in certain boot modes (notably QSPI boot). Attempting to configure the PL with the loopback bit set will result in timeouts and will prevent successful configuration. In order to avoid this problem, and to avoid dependency on the version of the FSBL used to boot the system, ensure that the loopback enable bit is cleared when loading the driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* fpga: zynqpl: Add support for zc7100 device.Michal Simek2013-08-12-1/+1
| | | | | | | | | | - Add support for zc7100 device. - FPGA programming on few of the SOC(zc7100) takes more than 1sec, hence increased the program time by 4sec to sync' all soc's. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* fpga: zynq: Add support for loading bitstreamMichal Simek2013-05-06-0/+355
Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
generated by cgit v1.1 at 2024-12-29 04:21:29 +0000