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* powerpc: MPC8555: Remove macro CONFIG_MPC8555York Sun2016-11-23-2/+2
| | | | | | | Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: mpc8541: Remove macro CONFIG_MPC8541York Sun2016-11-23-2/+2
| | | | | | | Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* ddr: altera: Configuring SDRAM extra cycles timing parametersChin Liang See2016-10-27-0/+3
| | | | | | | | | | To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* Various, accumulated typos collected from around the tree.Robert P. J. Day2016-10-06-1/+1
| | | | | | | | | | | | | | | | | | | | | Fix various misspellings of: * deprecated * partition * preceding,preceded * preparation * its versus it's * export * existing * scenario * redundant * remaining * value * architecture Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Stefan Roese <sr@denx.de>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-26-40/+213
|\ | | | | | | | | | | | | trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * driver: ddr: fsl_mmdc: Pass board parameters through data structureYork Sun2016-09-26-19/+19
| | | | | | | | | | | | | | | | | | Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * ddr: fsl: fix a compile issueShaohui Xie2016-09-14-1/+6
| | | | | | | | | | | | | | | | | | | | When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that temp32 undeclared, this patch fixes it. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu2016-09-14-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Revise workaround A008511 for A009803York Sun2016-09-14-36/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR controller 5.2.1 has this erratum A008511 partially fixed. The workaround needs to be adjusted to take advantage of Vref training. This patch enables the training and force output enable to be off. Erratum A009803 requires the controller to be idel before enabling address parity. It was combined with workaround for A008511. With new A008511 flow, this flow needs to be changed to enabling data init (D_INIT) after the address parity is enabled. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * driver/ddr/fsl: Add more debug registersYork Sun2016-09-14-3/+3
| | | | | | | | | | | | | | 32 more debug registers are added for newer DDR controllers. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
* | drivers: squash lines for immediate returnMasahiro Yamada2016-09-23-25/+5
|/ | | | | | Remove unneeded variables and assignments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* driver/ddr/fsl: Fix timing_cfg_2York Sun2016-08-02-1/+1
| | | | | | | | | Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the change was wrong. wr_lat has 5 bits with MSB at [13] and lower 4 bits at [9:12], in big-endian convention. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>
* Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-1/+1
| | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* driver/ddr/fsl: Check condition for erratum A-009803Shengzhou Liu2016-06-03-19/+23
| | | | | | | | | Add condition of checking the enabled of address parity for erratum A-009803, if parity is not enabled, the workaround of erratum A-009803 should not be applied. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* drivers/ddr/fsl: Disabling data init if ECC is not enabledYork Sun2016-06-03-1/+2
| | | | | | If ECC is not enabled, data init can be disabled to speed up booting. Signed-off-by: York Sun <york.sun@nxp.com>
* drivers/ddr/fsl: Fix timing_cfg_2 registerYork Sun2016-06-03-1/+1
| | | | | | | | | Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but with wrong bit position. It is bit 13 in big-endian, or left shift 18 from LSB. This error hasn't had any impact because we don't have fast enough DDR4 using the extra bit so far. Signed-off-by: York Sun <york.sun@nxp.com>
* drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntlShengzhou Liu2016-06-03-2/+9
| | | | | | | | | The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series, but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs. We should update it to adapt the case that clk_adjust is odd data. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-24-4/+23
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| * driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu2016-05-18-1/+9
| | | | | | | | | | | | | | | | | | During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu2016-05-17-0/+7
| | | | | | | | | | | | | | | | The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * drivers/ddr/fsl: update workaround for erratum A-008511Shengzhou Liu2016-05-17-3/+7
| | | | | | | | | | | | | | | | Per the latest erratum document, update step 4 and step 8, only DEBUG_29[21] is changed, all other bits should not be changed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm: mvebu: a38x: Weed out floating point useMarek Vasut2016-05-20-19/+10
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For reason unknown, recently, the DDR init code writers are really fond of hiding some small floating point operating deep in their creations. This patch removes one from the Marvell A38x code. Instead of returning size of chip as float from ddr3_get_device_size() in GiB units, return it as int in MiB units. Since this would interfere with the huge switch code in ddr3_calc_mem_cs_size(), rework the code to match the change. Before this patch, the cs_mem_size variable could have these values: ( { 16, 32 } x { 8, 16 } x { 0.01, 0.5, 1, 2, 4, 8 } ) / 8 = { 0.000000, 0.001250, 0.002500, 0.005000, 0.062500, 0.125000, 0.250000, 0.500000, 1.000000, 2.000000, 4.000000, } The switch code checked for a subset of the resulting RAM sizes, which is in range 128 MiB ... 2048 MiB. With this patch, the cs_mem_size variable can have these values: ( { 16, 32 } x { 8, 16 } x { 0, 512, 1024, 2048, 4096, 8192 } ) / 8 = { 0, 64, 128, 256, 512, 1024, 2048, 4096 } To retain previous behavior, filter out 0 MiB (invalid size), 64 MiB and 4096 MiB options. Removing the floating point stuff also saves 1.5k from text segment: clearfog : spl/u-boot-spl:all -1592 spl/u-boot-spl:text -1592 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Fix spelling of "occurred".Vagrant Cascadian2016-05-02-2/+2
| | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* ddr: altera: Repair DQ window centering codeMarek Vasut2016-04-20-8/+7
| | | | | | | | | | | | The code uses a lot of signed numbers, which ended up in variables of unsigned type, which resulted in all sorts of underflows. This in turn caused incorrect calibration on certain boards. Moreover, repair the readout of the DQ delay, which was being pulled from wrong register. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Staticize global variablesMarek Vasut2016-04-20-4/+4
| | | | | | | | | Just staticize global variables in sequencer, since there is no point in having these symbols available outside of the DDR code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Make DLEVEL behavior inclusiveMarek Vasut2016-04-20-66/+66
| | | | | | | | | | | | Originally, the DLEVEL selects the debug level within the sequencer code, but only displays the messages on that particular debug level. Tweak the handling such that for particular debug level, debug messages on that level and lower are displayed. This allows better regulation of debug message verbosity. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Zero DM IN delay in scc_mgr_zero_group()Marek Vasut2016-04-20-3/+13
| | | | | | | | | This one last set of delay configuration registers was not properly zeroed out originally, fix it and zero them out. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Remove unnecessary ODT mode configMarek Vasut2016-04-20-1/+0
| | | | | | | | | | | There is no point in resetting the ODT setting if the write test failed, since the code will always retry the calibration and thus reconfigure the ODT anyway OR the code will fail calibration and halt. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Remove unnecessary update of the SCCMarek Vasut2016-04-20-1/+0
| | | | | | | | | | | Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is followed by SCC manager update. Moreover, only this function triggers the SCC manager update internally. Thus, remove the internal invocation to avoid triggering the update twice. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Fix DRAM end value in protection ruleMarek Vasut2016-04-20-1/+1
| | | | | | | | | | The hi address bitfield in the protection rule must be set to the last address in the region which the rule represents. The behavior is now in-line with code generated by Quartus 15.1 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Fix scc_mgr_set() argument orderMarek Vasut2016-04-20-1/+1
| | | | | | | | | | The code should be setting registers to zero, not one register to value. Swap the order of arguments to correct the behavior. The behavior is now in-line with code generated by Quartus 15.1 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Tweak DQS tracking enable handlingMarek Vasut2016-04-20-2/+5
| | | | | | | | | | In the most unlikely case the DQS tracking was to be disabled, make sure we do not errornously re-enable it. Note that DQS tracking is enabled on all systems observed thus far. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Replace ad-hoc constant with macroMarek Vasut2016-04-20-2/+2
| | | | | | | | | The bit 22 is in fact DQS tracking enable bit (dqstrken) and there is a macro for this bit already, so use it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* Fix typo choosen in comments and printf logsAlexander Merkle2016-03-27-2/+2
| | | | | | | | Minor change: chosen is written with one "o". No code change here, only comment & printf. Signed-off-by: Alexander Merkle <alexander.merkle@lauterbach.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: mvebu: Fix ddr3_init() cpu configDirk Eibach2016-03-24-2/+0
| | | | | | | | Armada 38x has a maximum of two cores. Probably copy/paste bug from Armada XP. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu2016-03-21-5/+39
| | | | | | | | | During initial DDR training, false parity errors may be detected. This patch adds workaround to fix the erratum. Tested on LS2085QDS and LS2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discreteShengzhou Liu2016-03-21-7/+63
| | | | | | | | | | Add support of address parity for DDR4 UDIMM or discrete memory. It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig, e.g. hwconfig=fsl_ddr:parity=on. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Use correct spelling of "U-Boot"Bin Meng2016-02-06-1/+1
| | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+497
| | | | | | | | | | | This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllersEd Swarthout2016-01-25-0/+1
| | | | | | | | Following commit 61bd2f75, exclude unused DDR controller from calculating RAM size for SPL boot. Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver/ddr/fsl: Add workaround for A009663Shengzhou Liu2016-01-25-0/+10
| | | | | | | | | | | | Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl/ddr: Add workaround for ERRATUM_A009942Shengzhou Liu2016-01-25-0/+18
| | | | | | | | | | | | During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Add more SPDX-License-Identifier tagsTom Rini2016-01-19-30/+10
| | | | | | | | | In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
* ddr: altera: Init the rule ID in debug codeMarek Vasut2016-01-16-0/+1
| | | | | | | | | | Init the rule ID, otherwise the debug code will always dump the protection settings entry 0. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com>
* mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BITPhil Sutter2016-01-14-11/+11
| | | | | | | | | This should make it clear that this symbol is meant to be defined by board headers. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* axp: Fix debugging support in DDR3 write levelingPhil Sutter2016-01-14-2/+2
| | | | | | | | | | If MV_DEBUG_WL is defined, DEBUG_WL_S and DEBUG_WL_D macros are missing. In addition to that, get rid of debug output printing non-existent counter variable. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: mvebu: Make ECC support configurable on Armada XPStefan Roese2016-01-14-0/+8
| | | | | | | | | | | Currently, ECC support is enabled for all Armada XP boards. So the DDR3 driver tries to configure the controller with ECC support, even on boards without ECC. This patch makes this ECC optional which now can be configured on a board-per-board basis. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc>
* arm: mvebu: ddr: Fix compilation warningStefan Roese2016-01-14-17/+0
| | | | | | | | | | | | | | | | | | gcc 5.1 generates this new warning (for Armada 38x platforms): drivers/ddr/marvell/a38x/ddr3_debug.c: In function 'hws_ddr3_tip_read_training_result': drivers/ddr/marvell/a38x/ddr3_debug.c:177:40: warning: 'sizeof' on array function parameter 'result' will return size of 'enum hws_result (*)[1]' [-Wsizeof-array-argument] memcpy(result, training_result, sizeof(result)); ^ drivers/ddr/marvell/a38x/ddr3_debug.c:171:31: note: declared here u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]) ^ Since this functions is not referenced anywhere, lets just remove it. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* move erratum a008336 and a008514 to soc specific fileYao Yuan2015-12-15-34/+0
| | | | | | | | As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl/ddr: updated ddr errata-A008378 for arm and power SoCsShengzhou Liu2015-12-13-3/+6
| | | | | | | | | DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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