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* driver/ddr/fsl: Fix timing_cfg_2York Sun2016-08-02-1/+1
* Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-1/+1
* driver/ddr/fsl: Check condition for erratum A-009803Shengzhou Liu2016-06-03-19/+23
* drivers/ddr/fsl: Disabling data init if ECC is not enabledYork Sun2016-06-03-1/+2
* drivers/ddr/fsl: Fix timing_cfg_2 registerYork Sun2016-06-03-1/+1
* drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntlShengzhou Liu2016-06-03-2/+9
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-24-4/+23
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| * driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu2016-05-18-1/+9
| * driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu2016-05-17-0/+7
| * drivers/ddr/fsl: update workaround for erratum A-008511Shengzhou Liu2016-05-17-3/+7
* | arm: mvebu: a38x: Weed out floating point useMarek Vasut2016-05-20-19/+10
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* Fix spelling of "occurred".Vagrant Cascadian2016-05-02-2/+2
* ddr: altera: Repair DQ window centering codeMarek Vasut2016-04-20-8/+7
* ddr: altera: Staticize global variablesMarek Vasut2016-04-20-4/+4
* ddr: altera: Make DLEVEL behavior inclusiveMarek Vasut2016-04-20-66/+66
* ddr: altera: Zero DM IN delay in scc_mgr_zero_group()Marek Vasut2016-04-20-3/+13
* ddr: altera: Remove unnecessary ODT mode configMarek Vasut2016-04-20-1/+0
* ddr: altera: Remove unnecessary update of the SCCMarek Vasut2016-04-20-1/+0
* ddr: altera: Fix DRAM end value in protection ruleMarek Vasut2016-04-20-1/+1
* ddr: altera: Fix scc_mgr_set() argument orderMarek Vasut2016-04-20-1/+1
* ddr: altera: Tweak DQS tracking enable handlingMarek Vasut2016-04-20-2/+5
* ddr: altera: Replace ad-hoc constant with macroMarek Vasut2016-04-20-2/+2
* Fix typo choosen in comments and printf logsAlexander Merkle2016-03-27-2/+2
* arm: mvebu: Fix ddr3_init() cpu configDirk Eibach2016-03-24-2/+0
* driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu2016-03-21-5/+39
* driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discreteShengzhou Liu2016-03-21-7/+63
* Use correct spelling of "U-Boot"Bin Meng2016-02-06-1/+1
* drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+497
* drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllersEd Swarthout2016-01-25-0/+1
* driver/ddr/fsl: Add workaround for A009663Shengzhou Liu2016-01-25-0/+10
* fsl/ddr: Add workaround for ERRATUM_A009942Shengzhou Liu2016-01-25-0/+18
* Add more SPDX-License-Identifier tagsTom Rini2016-01-19-30/+10
* ddr: altera: Init the rule ID in debug codeMarek Vasut2016-01-16-0/+1
* mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BITPhil Sutter2016-01-14-11/+11
* axp: Fix debugging support in DDR3 write levelingPhil Sutter2016-01-14-2/+2
* arm: mvebu: Make ECC support configurable on Armada XPStefan Roese2016-01-14-0/+8
* arm: mvebu: ddr: Fix compilation warningStefan Roese2016-01-14-17/+0
* move erratum a008336 and a008514 to soc specific fileYao Yuan2015-12-15-34/+0
* fsl/ddr: updated ddr errata-A008378 for arm and power SoCsShengzhou Liu2015-12-13-3/+6
* driver/ddr/fsl: Update timing config for heavy loadYork Sun2015-12-13-2/+24
* driver/ddr/fsl: Update workaround for A008511 for vref rangeYork Sun2015-12-13-7/+15
* driver/ddr/fsl: Update MR5 RTT parkYork Sun2015-12-13-4/+15
* driver/ddr/fsl: Update DDR4 MR6 for Vref rangeYork Sun2015-12-13-0/+3
* driver/ddr/fsl: Update DDR4 RTT valuesYork Sun2015-12-13-2/+235
* drivers/ddr/fsl: Fix typo in BIST test for DDR4York Sun2015-11-30-12/+12
* drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3York Sun2015-11-30-0/+41
* armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha2015-11-30-2/+2
* armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha2015-11-30-2/+2
* arm: mvebu: Fix SAR1_CPU_CORE_MASKDirk Eibach2015-11-17-5/+2
* arm: mvebu: a38x: Remove unsupported topologiesKevin Smith2015-11-17-77/+0
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