index
:
arm-boot/u-boot-imx.git
imx_3.14.38_6ul_engr
imx_v2009.08
imx_v2009.08_1.1.0
imx_v2009.08_10.04.01
imx_v2009.08_10.05.02
imx_v2009.08_10.07.11
imx_v2009.08_10.10.01
imx_v2009.08_10.11.01
imx_v2009.08_10.12.01
imx_v2009.08_11.04.01
imx_v2009.08_11.05.01
imx_v2009.08_11.09.01
imx_v2009.08_11.11.01
imx_v2009.08_12.01.01
imx_v2009.08_12.02.01
imx_v2009.08_12.09.01
imx_v2009.08_12.10.02
imx_v2009.08_3.0.0
imx_v2009.08_3.0.35_4.0.0
imx_v2009.08_3.0.35_4.1.0
imx_v2009.08_r13.4.y
imx_v2013.04_3.10.17_1.0.0_beta
imx_v2013.04_3.10.17_1.0.0_ga
imx_v2013.04_3.10.31_1.1.0_alpha
imx_v2013.04_3.10.9_1.0.0_alpha
imx_v2013.04_3.5.7_1.0.0_alpha
imx_v2014.04_3.10.31_1.1.0_beta
imx_v2014.04_3.10.31_1.1.0_beta2
imx_v2014.04_3.10.53_1.1.0_ga
imx_v2014.04_3.14.28_1.0.0_ga
imx_v2014.04_3.14.28_7d_alpha
imx_v2014.04_3.14.38_6qp_beta
imx_v2014.04_kk4.4.3_2.y
imx_v2015.04
imx_v2015.04_3.14.38_6qp_ga
imx_v2015.04_3.14.38_6ul7d_beta
imx_v2015.04_3.14.38_6ul_ga
imx_v2015.04_3.14.52_1.1.0_ga
imx_v2015.04_4.1.15_1.0.0_ga
imx_v2015.04_brillo
imx_v2016.03_4.1.15_2.0.0_ga
imx_v2016.03_4.1.30_7ulp_alpha
imx_v2016.03_4.1.33_7ulp_beta
imx_v2017.03_4.9.11_1.0.0_ga
isee_imx_v2017.03_4.9.11_1.0.0_ga
isee_imx_v2017.03_4.9.11_1.0.0_ga_TEST
maddev-imx-android-r10.3
maddev-imx-android-r13.2
master
scm-imx_v2016.03_4.1.15_2.0.0_ga
U-boot NXP imx6
git@iatec.biz
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path:
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drivers
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ddr
Commit message (
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Author
Age
Lines
...
*
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue()
Marek Vasut
2015-08-08
-13
/
+18
*
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3
Marek Vasut
2015-08-08
-1
/
+11
*
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2
Marek Vasut
2015-08-08
-39
/
+36
*
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1
Marek Vasut
2015-08-08
-205
/
+201
*
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5
Marek Vasut
2015-08-08
-1
/
+6
*
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4
Marek Vasut
2015-08-08
-6
/
+7
*
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3
Marek Vasut
2015-08-08
-3
/
+2
*
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2
Marek Vasut
2015-08-08
-79
/
+88
*
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1
Marek Vasut
2015-08-08
-61
/
+63
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11
Marek Vasut
2015-08-08
-1
/
+10
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10
Marek Vasut
2015-08-08
-4
/
+7
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9
Marek Vasut
2015-08-08
-18
/
+17
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8
Marek Vasut
2015-08-08
-18
/
+15
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7
Marek Vasut
2015-08-08
-12
/
+9
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6
Marek Vasut
2015-08-08
-89
/
+88
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5
Marek Vasut
2015-08-08
-46
/
+44
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4
Marek Vasut
2015-08-08
-17
/
+23
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3
Marek Vasut
2015-08-08
-66
/
+60
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2
Marek Vasut
2015-08-08
-170
/
+146
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1
Marek Vasut
2015-08-08
-221
/
+197
*
ddr: altera: Clean up rw_mgr_mem_calibrate_writes()
Marek Vasut
2015-08-08
-12
/
+24
*
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5
Marek Vasut
2015-08-08
-4
/
+13
*
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4
Marek Vasut
2015-08-08
-9
/
+11
*
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3
Marek Vasut
2015-08-08
-4
/
+3
*
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2
Marek Vasut
2015-08-08
-15
/
+15
*
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1
Marek Vasut
2015-08-08
-13
/
+16
*
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks()
Marek Vasut
2015-08-08
-15
/
+25
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 7
Marek Vasut
2015-08-08
-0
/
+6
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 6
Marek Vasut
2015-08-08
-17
/
+14
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 5
Marek Vasut
2015-08-08
-6
/
+6
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 4
Marek Vasut
2015-08-08
-54
/
+49
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3
Marek Vasut
2015-08-08
-2
/
+3
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 2
Marek Vasut
2015-08-08
-10
/
+0
*
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 1
Marek Vasut
2015-08-08
-80
/
+70
*
ddr: altera: Clean up find_vfifo_read()
Marek Vasut
2015-08-08
-19
/
+18
*
ddr: altera: Clean up rw_mgr_*_vfifo() part 2
Marek Vasut
2015-08-08
-51
/
+41
*
ddr: altera: Clean up rw_mgr_*_vfifo() part 1
Marek Vasut
2015-08-08
-4
/
+18
*
ddr: altera: Clean up sdr_*_phase() part 10
Marek Vasut
2015-08-08
-17
/
+42
*
ddr: altera: Clean up sdr_*_phase() part 9
Marek Vasut
2015-08-08
-11
/
+11
*
ddr: altera: Clean up sdr_*_phase() part 8
Marek Vasut
2015-08-08
-6
/
+3
*
ddr: altera: Clean up sdr_*_phase() part 7
Marek Vasut
2015-08-08
-5
/
+6
*
ddr: altera: Clean up sdr_*_phase() part 6
Marek Vasut
2015-08-08
-31
/
+9
*
ddr: altera: Clean up sdr_*_phase() part 5
Marek Vasut
2015-08-08
-55
/
+72
*
ddr: altera: Clean up sdr_*_phase() part 4
Marek Vasut
2015-08-08
-31
/
+10
*
ddr: altera: Clean up sdr_*_phase() part 3
Marek Vasut
2015-08-08
-9
/
+12
*
ddr: altera: Clean up sdr_*_phase() part 2
Marek Vasut
2015-08-08
-20
/
+20
*
ddr: altera: Clean up sdr_*_phase() part 1
Marek Vasut
2015-08-08
-3
/
+3
*
ddr: altera: Clean up sdr_find_window_centre() part 3
Marek Vasut
2015-08-08
-15
/
+20
*
ddr: altera: Clean up sdr_find_window_centre() part 2
Marek Vasut
2015-08-08
-16
/
+15
*
ddr: altera: Clean up sdr_find_window_centre() part 1
Marek Vasut
2015-08-08
-32
/
+32
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