summaryrefslogtreecommitdiff
path: root/drivers/ddr/fsl
Commit message (Collapse)AuthorAgeLines
* driver/ddr/fsl: Add workaround for DDR erratum A008511York Sun2015-04-23-1/+95
| | | | | | | | This erratum only applies to general purpose DDR controllers in LS2. It shouldn't be applied to DP-DDR controller. Check DDRC versoin number before applying workaround. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add built-in memory test for DDR4 driverYork Sun2015-04-23-0/+73
| | | | | | | | | Add built-in memory test to catch errors after DDR is initialized, before any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST. An environmental variable "ddr_bist" is checked before starting test. It takes a while (several seconds) depending on system memory size. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Fix driver to support empty first slotYork Sun2015-04-23-28/+56
| | | | | | | | CS0 was not allowed to be empty by u-boot driver in the past to simplify the driver. This may be inconvenient for some debugging. This patch lifts the restrictions. Controller interleaving still requires CS0 populated. Signed-off-by: York Sun <yorksun@freescale.com>
* drivers/ddr/fsl: Update DDR driver for DDR4York Sun2015-04-23-10/+88
| | | | | | | | | | Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun <yorksun@freescale.com>
* MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT registerCurt Brune2015-04-20-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the MPC8555/MPC8541 reference manual the SS_EN (source synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set during initialization. >From section 9.4.1.8 of that manual: Source synchronous enable. This bit field must be set during initialization. See Section 9.6.1, "DDR SDRAM Initialization Sequence," details. 0 - Reserved 1 - The address and command are sent to the DDR SDRAMs source synchronously. In addition, Freescale application note AN2805 is also very clear that this bit must be set. This patch reverts a change introduced by commit 457caecdbca3df21a93abff19eab12dbc61b7897. Testing Done: Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS and inspected the generated assembly code to verify the SS_EN bit was being set. There is one extra instruction emitted: fff9b774: 65 29 80 00 oris r9,r9,32768 Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no additional instructions were emitted related to this patch. Booted an image on a MPC8541 based board successfully. Signed-off-by: Curt Brune <curt@cumulusnetworks.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add sync of refreshYork Sun2015-02-24-0/+59
| | | | | | | Add sync of refresh for multiple DDR controllers. DDRC initialization needs to complete first. Code is re-ordered to keep refresh close. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Fix a typo in timing_cfg_8 calculationYork Sun2015-02-24-1/+1
| | | | | | wwt_bg should match rrt_bg. It was a typo in driver. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add support for multiple DDR clocksYork Sun2015-02-24-152/+180
| | | | | | | | | Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add workround for erratumn A008514York Sun2015-02-24-5/+17
| | | | | | | Erratum A008514 workround requires writing register eddrtqcr1 with value 0x63b20002. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add workaround for A008336York Sun2015-02-24-0/+22
| | | | | | | Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space for 64-bit DDR controllers. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Adjust CAS to preamble override for emulatorYork Sun2015-02-24-1/+5
| | | | | | | | | On ZeBu emulator, CAS to preamble overrides need to be set to satisfy the timing. This only impact platforms with CONFIG_EMU. These should be set before MEM_EN is set. Signed-off-by: York Sun <yorksun@freescale.com>
* arm/ls1021a: Add workaround for DDR erratum A008378York Sun2015-01-23-0/+8
| | | | | | | Internal memory controller counters can reach a bad state after training in DDR4 mode if accumulated ECC or DBI mode is eanbled. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Fix MRC_CYC calculation for DDR3York Sun2014-12-15-1/+20
| | | | | | | | | | For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun <yorksun@freescale.com>
* fsl/sleep: updated the deep sleep framework for QorIQ platformsTang Yuantian2014-12-11-53/+103
| | | | | | | | | | | | | With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add workaround for faulty SPDYork Sun2014-12-05-0/+22
| | | | | | | Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39]. Using raw card spec in case this error is detected. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slotsYork Sun2014-12-05-6/+25
| | | | | | | | | Increase write-to-write and read-to-read turnaround time for two-slot DDR configurations. Previously only quad-rank and two dual-rank configurations have this additional turnaround time. A recent test on two single-rank DIMMs shows the shorter additional turnaround time is also needed. Signed-off-by: York Sun <yorksun@freescale.com>
* linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2014-11-23-38/+49
| | | | | | | | | | | | | | | | | | | | U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
* driver/ddr/fsl: Fix DDR4 driverYork Sun2014-09-25-4/+8
| | | | | | | | | | | When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Fix tXP and tCKEYork Sun2014-09-25-12/+22
| | | | | | | | The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr: Restruct driver to allow standalone memory spaceYork Sun2014-09-25-100/+205
| | | | | | | | | | U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add support of overriding chip select write levelingYork Sun2014-09-08-0/+5
| | | | | | | | | | JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/freescale: Fix DDR3 driver for ARMYork Sun2014-09-08-1/+1
| | | | | | | Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/freescale: Add support of accumulate ECCYork Sun2014-09-08-0/+5
| | | | | | | | | If less than 8 ECC pins are used for DDR data bus width smaller than 64 bits, the 8-bit ECC code will be transmitted/received across several beats, and it will be used to check 64-bits of data once 8-bits of ECC are accumulated. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr: Fix DDR register timing_cfg_8York Sun2014-07-22-0/+3
| | | | | | | The field wrtord_bg should add 2 clocks if on the fly chop is enabled, according to DDR controller manual for DDR4. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr: Fix DDR4 driver for ARMYork Sun2014-07-22-2/+5
| | | | | | | Previously the driver was only tested on Power SoCs. Different barrier instructions are needed for ARM SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Fix printing unspecified module info for DDR4York Sun2014-06-05-1/+1
| | | | | | The offset of module information is at 128, different from DDR3. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Add workaround for DDR erratum A004508York Sun2014-06-05-0/+5
| | | | | | | | | | | When the DDR controller is initialized below a junction temperature of 0°C and then operated above a junction temperature of 65°C, the DDR controller may cause receive data errors, resulting ECC errors and/or corrupted data. This erratum applies to the following SoCs and their variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023, P2020. Signed-off-by: York Sun <yorksun@freescale.com>
* Add cli_ prefix to readline functionsSimon Glass2014-05-29-3/+4
| | | | | | This makes it clear where the code resides. Signed-off-by: Simon Glass <sjg@chromium.org>
* move CLI prototypes to cli.h and add commentsSimon Glass2014-05-29-0/+1
| | | | | | | Move the CLI prototypes from common.h to cli.h as part of an effort to reduce the size of common.h. Signed-off-by: Simon Glass <sjg@chromium.org>
* mpc85xx/t104x: Add deep sleep framework supportTang Yuantian2014-04-22-4/+48
| | | | | | | | | | When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers/ddr: Fix possible out of bounds errorYork Sun2014-04-22-58/+64
| | | | | | | | | This is a theoretical possible out of bounds error in DDR driver. Adding check before using array index. Also change some runtime conditions to pre-compiling conditions. Signed-off-by: York Sun <yorksun@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add DDR4 support to Freescale DDR driverYork Sun2014-04-22-269/+1906
| | | | | | | Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr: Add 256 byte interleaving supportYork Sun2014-02-21-2/+20
| | | | | | | Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/ddr: Add support of different DDR base addressYork Sun2014-02-21-2/+14
| | | | | | | | | DDR base address has been the same from the view of core and DDR controllers. This has changed for Freescale ARM-based SoCs. Controllers setup DDR memory in a contiguous space and cores view it at separated locations. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr: Change Freescale ARM DDR driver to support both big and little ↵York Sun2014-02-21-59/+60
| | | | | | | | | endian Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Revise workaround for DDR-A003York Sun2014-01-21-2/+67
| | | | | | | | | | | | Existing workaround only handles one RDIMM on reference design. In case of two RDIMMs being used, the workaround requires two separate writes to DDR_SDRAM_MD_CNTL register. This patch also restores two debug registers changed by the workaround. Signed-off-by: York Sun <yorksun@freescale.com> CC: Ben Collins <ben.c@servergy.com> CC: James Yang <James.Yang@freescale.com>
* Driver/DDR: Update DDR driver to allow non-zero base addressYork Sun2013-11-25-3/+3
| | | | | | | The DRAM base has been zero for Power SoCs. It could be non-zero for ARM SoCs. Use a macro instead of hard-coding to zero. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Extend DDR registers' fieldsYork Sun2013-11-25-8/+12
| | | | | | | | | | | Some DDR registers' fields have expanded to accommodate larger values. These changes are backward compatible. Some fields are removed for newer DDR controllers. Writing to those fields are safely ignored. TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE automatically. It was a misunderstanding in commit c360ceac. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Add Freescale DDR driver for ARMYork Sun2013-11-25-4/+227
| | | | | | | Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xxYork Sun2013-11-25-8/+14
| | | | | | | Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-0/+7977
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-05 14:02:21 +0000