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* driver/ddr: Add 256 byte interleaving supportYork Sun2014-02-21-2/+20
| | | | | | | Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/ddr: Add support of different DDR base addressYork Sun2014-02-21-2/+14
| | | | | | | | | DDR base address has been the same from the view of core and DDR controllers. This has changed for Freescale ARM-based SoCs. Controllers setup DDR memory in a contiguous space and cores view it at separated locations. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr: Change Freescale ARM DDR driver to support both big and little ↵York Sun2014-02-21-59/+60
| | | | | | | | | endian Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Revise workaround for DDR-A003York Sun2014-01-21-2/+67
| | | | | | | | | | | | Existing workaround only handles one RDIMM on reference design. In case of two RDIMMs being used, the workaround requires two separate writes to DDR_SDRAM_MD_CNTL register. This patch also restores two debug registers changed by the workaround. Signed-off-by: York Sun <yorksun@freescale.com> CC: Ben Collins <ben.c@servergy.com> CC: James Yang <James.Yang@freescale.com>
* Driver/DDR: Update DDR driver to allow non-zero base addressYork Sun2013-11-25-3/+3
| | | | | | | The DRAM base has been zero for Power SoCs. It could be non-zero for ARM SoCs. Use a macro instead of hard-coding to zero. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Extend DDR registers' fieldsYork Sun2013-11-25-8/+12
| | | | | | | | | | | Some DDR registers' fields have expanded to accommodate larger values. These changes are backward compatible. Some fields are removed for newer DDR controllers. Writing to those fields are safely ignored. TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE automatically. It was a misunderstanding in commit c360ceac. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Add Freescale DDR driver for ARMYork Sun2013-11-25-4/+227
| | | | | | | Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xxYork Sun2013-11-25-8/+14
| | | | | | | Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-0/+7977
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
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