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path: root/drivers/ddr/fsl/main.c
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* driver/ddr/fsl: Add sync of refreshYork Sun2015-02-24-0/+4
| | | | | | | Add sync of refresh for multiple DDR controllers. DDRC initialization needs to complete first. Code is re-ordered to keep refresh close. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add support for multiple DDR clocksYork Sun2015-02-24-11/+14
| | | | | | | | | Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
* linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2014-11-23-1/+2
| | | | | | | | | | | | | | | | | | | | U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
* driver/ddr: Restruct driver to allow standalone memory spaceYork Sun2014-09-25-80/+164
| | | | | | | | | | U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun <yorksun@freescale.com>
* drivers/ddr: Fix possible out of bounds errorYork Sun2014-04-22-0/+6
| | | | | | | | | This is a theoretical possible out of bounds error in DDR driver. Adding check before using array index. Also change some runtime conditions to pre-compiling conditions. Signed-off-by: York Sun <yorksun@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add DDR4 support to Freescale DDR driverYork Sun2014-04-22-1/+24
| | | | | | | Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr: Add 256 byte interleaving supportYork Sun2014-02-21-0/+1
| | | | | | | Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/ddr: Add support of different DDR base addressYork Sun2014-02-21-2/+14
| | | | | | | | | DDR base address has been the same from the view of core and DDR controllers. This has changed for Freescale ARM-based SoCs. Controllers setup DDR memory in a contiguous space and cores view it at separated locations. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Update DDR driver to allow non-zero base addressYork Sun2013-11-25-3/+3
| | | | | | | The DRAM base has been zero for Power SoCs. It could be non-zero for ARM SoCs. Use a macro instead of hard-coding to zero. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Add Freescale DDR driver for ARMYork Sun2013-11-25-3/+9
| | | | | | | Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-0/+718
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
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