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* powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPLSumit Garg2016-07-21-0/+17
| | | | | | | | | | | | | | | | As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-1/+1
| | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* verified-boot: Minimal support for booting U-Boot proper from SPLTeddy Reed2016-06-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This allows a board to configure verified boot within the SPL using a FIT or FIT with external data. It also allows the SPL to perform signature verification without needing relocation. The board configuration will need to add the following feature defines: CONFIG_SPL_CRYPTO_SUPPORT CONFIG_SPL_HASH_SUPPORT CONFIG_SPL_SHA256 In this example, SHA256 is the only selected hashing algorithm. And the following booleans: CONFIG_SPL=y CONFIG_SPL_DM=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_OF_LIBFDT=y CONFIG_SPL_FIT_SIGNATURE=y Signed-off-by: Teddy Reed <teddy.reed@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Dannenberg <dannenberg@ti.com> Acked-by: Sumit Garg <sumit.garg@nxp.com>
* crypto/fsl: add support for multiple SEC engines initializationAlex Porosanu2016-05-18-115/+159
| | | | | | | | | For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator). Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: LS2080A: Consolidate LS2080A and LS2085AYork Sun2016-04-06-3/+3
| | | | | | | | | | | | LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* crypto/fsl: Make CAAM transactions cacheableSaksham Jain2016-03-29-0/+16
| | | | | | | | | | | | | | | | | | This commit solves CAAM coherency issue on ls2080. When caches are enabled and CAAM's DMA's AXI transcations are not made cacheable, Core reads/writes data from/to caches and CAAM does from main memory. This forces data flushes to synchronize various data structures. But even if any data in proximity of these structures is read by core, these structures again are fetched in caches. To avoid this problem, either all the data that CAAM accesses can be made cache line aligned or CAAM transcations can be made cacheable. So, this commit makes CAAM transcations as write back with write and read allocate. Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* crypto/fsl: Correct 64-bit write when MMU disabledSaksham Jain2016-03-29-4/+3
| | | | | | | | | | | When MMU is disabled, 64-bit write must be aligned at 64-bit boundary. Becaue the memory location is not guaranteed to be 64-bit aligned, the 64-bit write needs to be split into two 32-bit writes to avoid the alignment exception. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* drivers/crypto/fsl: define structures for PDBAneesh Bansal2016-03-21-0/+55
| | | | | | | | | | | Structures are defined for PDB (Protocol Data Blcks) for various operations. These structure will be used to add PDB data while creating the PDB descriptors. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> CC: Ulises Cardenas <raul.casas@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* drivers/crypto/fsl: add constructs for protocol descriptorsAneesh Bansal2016-03-21-0/+52
| | | | | | | | | | Construct APIs are added to create Protocol Descriptors for CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> CC: Ulises Cardenas <raul.casas@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* drivers/crypto/fsl: correct error checking in run_descriptorAneesh Bansal2016-03-21-1/+1
| | | | | | | | | When CAAM runs a descriptor and an error occurs, a non-zero value is set in Output Status Register. The if condition should check the status for a non-zero value. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/SECURE_BOOT: Add PAMU driverAneesh Bansal2016-02-24-0/+23
| | | | | | | | | | | | | | | | PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* drivers/crypto/fsl : Allocate output ring with size aligned to CACHELNE SIZERuchika Gupta2016-02-24-12/+18
| | | | | | | | | | | | | | | | The output ring needs to be invalidated before enqueuing the job to SEC. While allocation of space to output ring, it should be taken care that the size is cacheline size aligned inorder to prevent invalidating valid data. The patch also correct the method of aligning end of structs while flushing caches Since start = align(start_of_struct), it is incorrect to assign end = align(start + struct_size). It should instead be, end = align(start_of_struct + struct_size). Signed-off-by: Saksham Jain <saksham@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* imx: Refactoring CAAM Job Ring structure and Secure Memory for imx7Ulises Cardenas2016-02-21-9/+21
| | | | | | | | | | | | Refactored data structure for CAAM's job ring and Secure Memory to support i.MX7. The new memory map use macros to resolve SM's offset by version. This will solve the versioning issue caused by the new version of secure memory of i.MX7 Signed-off-by: Ulises Cardenas <raul.casas@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* drivers/crypto/fsl: fix endianness issue in RNGAneesh Bansal2015-12-15-6/+2
| | | | | | | | | | | | | | For Setting and clearing the bits in SEC Block registers sec_clrbits32() and sec_setbits32() are used which work as per endianness of CAAM block. So these must be used with SEC register address as argument. If the value is read in a local variable, then the functions will not behave correctly where endianness of CAAM and core is different. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> CC: Alex Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* crypto/fsl: SEC driver cleanup for 64 bit and endiannessAneesh Bansal2015-10-29-20/+107
| | | | | | | | | | | | | | | | | The SEC driver code has been cleaned up to work for 64 bit physical addresses and systems where endianess of SEC block is different from the Core. Changes: 1. Descriptor created on Core is modified as per SEC block endianness before the job is submitted. 2. The read/write of physical addresses to Job Rings will be depend on endianness of SEC block as 32 bit low and high part of the 64 bit address will vary. 3. The 32 bit low and high part of the 64 bit address in descriptor will vary depending on endianness of SEC. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Correct License and Copyright information on few filesRuchika Gupta2015-08-12-3/+1
| | | | | | | | | gpio.h - Added missing copyright in few files. rsa-mod-exp.h - Corrected copyright in the file. fsl_sec.h - Added missing license in files drivers/crypto/fsl/Makefile - Removed the incomplete GPLv2 license and replaced it with GPLv2+ license Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
* drivers: hierarchize drivers Kconfig menuMasahiro Yamada2015-08-12-0/+4
| | | | | | | | | | | The menuconfig for drivers are getting more and more cluttered and unreadable because too many entries are displayed in a single flat menu. Use hierarchic menu for each category. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Update to apply again in a few places, drop USB hunk] Signed-off-by: Tom Rini <trini@konsulko.com>
* drivers/crypto/fsl: clean-up - use fdt_setprop_u32 helperhoria.geanta@freescale.com2015-08-03-9/+8
| | | | | | Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers/crypto/fsl: fix snooping for write transactionshoria.geanta@freescale.com2015-08-03-4/+8
| | | | | | | | | | | | | | | | | | | | HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001. It has to be programmed to 4'b0010. For platforms that have HW coherency support: -PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes -ARM-based: the update fixes cache coherency issues, since IOMMU (SMMU) driver is not programmed to behave similar to PAMU Fixes: b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 and SHA1") Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers/crypto/fsl: fix "era" property value on LE platformshoria.geanta@freescale.com2015-08-03-2/+1
| | | | | | | | | | Use fdt_setprop_u32() instead of fdt_setprop(). Fixes: 0181937fa371a ("crypto/fsl: Add fixup for crypto node") Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers/crypto/fsl: enable raw data instead of von Neumann dataAlex Porosanu2015-08-03-1/+10
| | | | | | | | | | | | The sampling of the oscillator can be done in multiple modes for generating the entropy value. By default, this is set to von Neumann. This patch changes the sampling to raw data, since it has been discovered that the generated entropy has a better 'quality'. Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers/crypto/fsl: disable RNG oscillator maximum frequency checkAlex Porosanu2015-08-03-2/+2
| | | | | | | | | | | | | | | | | The rtfrqmax & rtfrqmin set the bounds of the expected frequency of the oscillator, when SEC runs at its maximum frequency. For certain platforms (f.i. T2080), the oscillator is very fast and thus if the SEC runs at a lower than normal frequency, the ring oscillator is incorrectly detected as being out of bounds. This patch effectively disables the maximum frequency check, by setting a high enough maximum allowable frequency for the oscillator. The reasoning behind this is that usually a broken oscillator will run too slow (i.e. not run at all) rather than run too fast. Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-03-05-1/+2
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| * rsa : Compile Modular Exponentiation files based on CONFIG_RSA_SOFTWARE_EXPgaurav rana2015-03-05-1/+2
| | | | | | | | | | | | | | | | | | | | Remove dependency of rsa_mod_exp from CONFIG_FIT_SIGNATURE. As rsa modular exponentiation is an independent module and can be invoked independently. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <yorksun@freescale.com>
* | imx6: Added DEK blob generator commandRaul Cardenas2015-03-02-7/+256
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's SEC block has built-in Data Encryption Key(DEK) Blob Protocol which provides a method for protecting a DEK for non-secure memory storage. SEC block protects data in a data structure called a Secret Key Blob, which provides both confidentiality and integrity protection. Every time the blob encapsulation is executed, a AES-256 key is randomly generated to encrypt the DEK. This key is encrypted with the OTP Secret key from SoC. The resulting blob consists of the encrypted AES-256 key, the encrypted DEK, and a 16-bit MAC. During decapsulation, the reverse process is performed to get back the original DEK. A caveat to the blob decapsulation process, is that the DEK is decrypted in secure-memory and can only be read by FSL SEC HW. The DEK is used to decrypt data during encrypted boot. Commands added -------------- dek_blob - encapsulating DEK as a cryptgraphic blob Commands Syntax --------------- dek_blob src dst len Encapsulate and create blob of a len-bits DEK at address src and store the result at address dst. Signed-off-by: Raul Cardenas <Ulises.Cardenas@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ulises Cardenas <ulises.cardenas@freescale.com> Signed-off-by: Ulises Cardenas-B45798 <Ulises.Cardenas@freescale.com>
* crypto/fsl - Add progressive hashing support using hardware acceleration.gaurav rana2015-02-25-1/+171
| | | | | | | | | | | Currently only normal hashing is supported using hardware acceleration. Added support for progressive hashing using hardware. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <yorksun@freescale.com>
* crypto/fsl: Make function names consistent for blob encapsulation/decapsulation.gaurav rana2015-02-25-2/+2
| | | | | | | | | | | | | | | | This patch does the following: 1. The function names for encapsulation and decapsulation were inconsitent in freescale's implementation and cmd_blob file. This patch corrects the issues. 2. The function protopye is also modified to change the length parameter from u8 to u32 to allow encapsulation and decapsulation of larger images. 3. Modified the description of km paramter in the command usage for better readability. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* DM: crypto/fsl - Add Freescale rsa DM driverRuchika Gupta2015-01-29-0/+129
| | | | | | | | | Driver added for RSA Modular Exponentiation using Freescale Hardware Accelerator CAAM. The driver uses UCLASS_MOD_EXP Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> CC: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* DM: crypto/rsa_mod_exp: Add rsa Modular Exponentiation DM driverRuchika Gupta2015-01-29-0/+83
| | | | | | | | | Add a new rsa uclass for performing modular exponentiation and implement the software driver basing on this uclass. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> CC: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* crypto/fsl: Add fixup for crypto nodeRuchika Gupta2015-01-23-0/+185
| | | | | | | | | | | Era property is added in the crypto node in device tree. Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to drivers/sec/sec.c so that it can be used across arm and powerpc platforms having crypto node. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> [York Sun: Fix commit message indentation] Reviewed-by: York Sun <yorksun@freescale.com>
* crypto/fsl: Fix RNG instantiation failure.gaurav rana2014-12-15-1/+1
| | | | | | | | | | Corrected the order of arguments in memset in run_descriptor function. Wrong order of argumnets led to improper initialization of members of struct type result. This resulted in RNG instantiation error. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* crypto/fsl: Add command for encapsulating/decapsulating blobsRuchika Gupta2014-10-16-1/+279
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's SEC block has built-in Blob Protocol which provides a method for protecting user-defined data across system power cycles. SEC block protects data in a data structure called a Blob, which provides both confidentiality and integrity protection. Encapsulating data as a blob Each time that the Blob Protocol is used to protect data, a different randomly generated key is used to encrypt the data. This random key is itself encrypted using a key which is derived from SoC's non volatile secret key and a 16 bit Key identifier. The resulting encrypted key along with encrypted data is called a blob. The non volatile secure key is available for use only during secure boot. During decapsulation, the reverse process is performed to get back the original data. Commands added -------------- blob enc - encapsulating data as a cryptgraphic blob blob dec - decapsulating cryptgraphic blob to get the data Commands Syntax --------------- blob enc src dst len km Encapsulate and create blob of data $len bytes long at address $src and store the result at address $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. blob dec src dst len km Decapsulate the blob of data at address $src and store result of $len byte at addr $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl_sec: Add hardware accelerated SHA256 and SHA1Ruchika Gupta2014-10-16-0/+1773
| | | | | | | | | | SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* kconfig: add blank Kconfig filesMasahiro Yamada2014-09-24-0/+0
| | | | | | | | This would be useful to start moving various config options. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* includes: move openssl headers to include/u-bootJeroen Hofstee2014-06-19-2/+2
| | | | | | | | | | | | commit 18b06652cd "tools: include u-boot version of sha256.h" unconditionally forced the sha256.h from u-boot to be used for tools instead of the host version. This is fragile though as it will also include the host version. Therefore move it to include/u-boot to join u-boot/md5.h etc which were renamed for the same reason. cc: Simon Glass <sjg@chromium.org> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* drivers: crypto: ace_sha: add implementation of hardware based lib randPrzemyslaw Marczak2014-03-28-4/+77
| | | | | | | | | | | | | | | | | | | | This patch adds implementation of rand library based on hardware random number generator of security subsystem in Exynos SOC. This library includes: - srand() - used for seed hardware block - rand() - returns random number - rand_r() - the same as above with given seed which depends on CONFIG_EXYNOS_ACE_SHA and CONFIG_LIB_HW_RAND. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> cc: Akshay Saraswat <akshay.s@samsung.com> cc: ARUN MANKUZHI <arun.m@samsung.com> cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Michael Walle <michael@walle.cc> Cc: Tom Rini <trini@ti.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
* drivers: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-24/+1
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-45/+3
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* Exynos: Add hardware accelerated SHA256 and SHA1Akshay Saraswat2013-03-29-0/+498
SHA-256 and SHA-1 accelerated using ACE hardware. Signed-off-by: ARUN MANKUZHI <arun.m@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
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