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* Merge git://git.denx.de/u-boot-dmTom Rini2017-02-08-10/+11
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| * dm: core: Replace of_offset with accessorSimon Glass2017-02-08-10/+11
| | | | | | | | | | | | | | | | | | At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
* | aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculationmaxims@google.com2017-02-08-2/+2
|/ | | | | | | | | Fix H-PLL and M-PLL rate calculation in ast2500 clock driver. Without this fix, valid setting can lead to division by zero when requesting the rate of H-PLL or M-PLL clocks. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: uniphier: fix compatible strings for Pro5, PXs2, LD20 SD clockMasahiro Yamada2017-01-29-3/+3
| | | | | | I missed to update them when DT files were resynced with Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* aspeed: Add basic ast2500-specific drivers and configurationmaxims@google.com2017-01-28-0/+274
| | | | | | | | | | | | | | | | | | | | | Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: zynqmp: Add clock driver support for zynqmpSiva Durga Prasad Paladugu2017-01-10-0/+249
| | | | | | | | | Add basic clock driver support for zynqmp which sets the required clock for GEM controller Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rockchip: clk: Support setting ACLKSimon Glass2016-11-25-0/+7
| | | | | | | | Add basic support for setting the ARM clock, since this allows us to run at maximum speed in U-Boot. Currently only a single speed is supported (1.8GHz). Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Move rockchip_get_cru() out of the driverSimon Glass2016-10-30-21/+0
| | | | | | | | This function is called from outside the driver. It should be placed into common SoC code. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3399: Move rockchip_get_cru() out of the driverSimon Glass2016-10-30-25/+1
| | | | | | | | | | | This function is called from outside the driver. It should be placed into common SoC code. Move it. Also rename the driver symbol to be more consistent with the other rockchip clock drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3036: Move rockchip_get_cru() out of the driverSimon Glass2016-10-30-23/+1
| | | | | | | | | | | This function is called from outside the driver. It should be placed into common SoC code. Move it. Also rename the driver symbol to be more consistent with the other rockchip clock drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* clk: rk3399: fix rockchip_get_cruJacob Chen2016-10-30-1/+3
| | | | | | | clk_rk3399 is driver name, not device name Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* clk: at91: Improve the clock implementationWenyou Yang2016-10-28-89/+195
| | | | | | | | | | | | | | | For the peripheral clock, provide the clock ops for the clock provider, such as spi0_clk. The .of_xlate is to get the clk->id, the .enable is to enable the spi0 peripheral clock, the .get_rate is to get the clock frequency. The driver for periph32ck node is responsible for recursively binding its children as clk devices, not provide the clock ops. So do the generated clock and system clock. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* clk: clk-uclass: Assign clk->dev before call .of_xlateWenyou Yang2016-10-28-0/+3
| | | | | | | | | | In order to make clk->dev available in ops->of_xlate() to get the clock ID from the 'reg' property of the clock node, assign the clk->dev before calling ops->of_xlate(). Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* clk: at91: Fix at91-pmc and at91-sckc's class IDWenyou Yang2016-10-28-20/+7
| | | | | | | | | | | The at91-pmc and at91-sckc aren't the clock providers, change their class ID from UCLASS_CLK to UCLASS_SIMPLE_BUS, they also don't need to bind the child nodes explicitly, the .post_bind callback of simple_bus uclass will do it for them. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: uniphier: rework UniPhier clk driverMasahiro Yamada2016-10-18-240/+179
| | | | | | | | The initial design of the UniPhier clk driver for U-Boot was not very nice. Here is a re-work to sync it with Linux's clk and reset drivers, maximizing the code reuse from Linux's clk data. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* libfdt: Bring in upstream stringlist functionsSimon Glass2016-10-13-3/+3
| | | | | | | | | | | | | | These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org>
* clock: implement a driver for the Tegra CARStephen Warren2016-09-27-0/+111
| | | | | | | | | | | | | | | | | Implement a clock uclass driver for the Tegra CAR. This allows clients to use standard clock APIs on Tegra. This device is intended to be instantiated by the core Tegra CAR driver, rather than being instantiated directly from DT. The implementation uses the existing custom Tegra- specific clock APIs to avoid coupling the series with significant refactoring of the existing Tegra clock/clock code. The driver currently only supports peripheral clocks, and avoids support for other clocks such as PLLs and external clocks. This should be sufficient to convert over all Tegra peripheral drivers, and avoids a complex implementation which calls different Tegra-specific clock APIs based on the type of clock being manipulated. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-09-22-4/+175
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| * clk: rk3288: add PWM clock get rateKever Yang2016-09-22-0/+2
| | | | | | | | | | | | | | This patch add clk_get_rate for PWM device. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * clk: rk3399: add pmucru controller supportKever Yang2016-09-22-4/+173
| | | | | | | | | | | | | | | | pmucru is a module like cru which is a clock controller manage some PLL and module clocks. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | clk: uniphier: allow to have clock node under syscon nodeMasahiro Yamada2016-09-23-9/+9
| | | | | | | | | | | | | | To sync the DT binding with Linux, the register base must be taken from the parent syscon node. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | clk: uniphier: move U_BOOT_DRIVER entry to core codeMasahiro Yamada2016-09-23-75/+74
| | | | | | | | | | | | | | | | Move U_BOOT_DRIVER() entry from the data file (clk-uniphier-mio.c) to the core support file (clk-uniphier-core.c) because I do not want to repeat the driver boilerplate when I add more clock data. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | clk: uniphier: constify clock data arrays/structuresMasahiro Yamada2016-09-23-9/+9
| | | | | | | | | | | | Clarify these clock data are constant. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | clk: boston: Providea simple driver for Boston board clocksPaul Burton2016-09-21-0/+106
|/ | | | | | | | | | Add a simple driver for the clocks provided by the MIPS Boston development board. The system provides information about 2 clocks whose rates are fixed by the bitfile flashed in the boards FPGA, and this driver simply reads the rates of these 2 clocks. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-08-15-0/+776
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| * clk: at91: Add clock driverWenyou Yang2016-08-15-0/+776
| | | | | | | | | | | | | | | | The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | clock: add Tegra186 clock driverStephen Warren2016-08-15-0/+118
|/ | | | | | | | | | | | In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. A tegra/ sub-directory is created to follow the existing pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* rockchip: remove log2 reimplementation from clock driversHeiko Stübner2016-08-05-14/+6
| | | | | | | | | The already available ilog2 function does exactly the same in the common case than the log2 function the current clock-driver reimplement. So, simply move to that one. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* clock: rk3399: add support for dwmmc 400KKever Yang2016-08-05-8/+21
| | | | | | | | | MMC core will use 400KHz for card initialize first and then switch to higher frequency like 50MHz, we need to support both 400KHz and about 50MHz for dwmmc controller. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* move: rockchip: move clock drivers into a subdirectoryHeiko Stübner2016-08-05-3/+10
| | | | | | | | | | | | With the number of Rockchip clock drivers increasing, don't clutter up the core drivers/clk directory with them and instead move them out of the way into a separate subdirectory. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org> Updated for rk3399: Signed-off-by: Simon Glass <sjg@chromium.org>
* rk3399: add basic soc driverKever Yang2016-08-05-0/+820
| | | | | | | | | | This patch add driver for: - clock driver including set_rate for cpu, mmc, vop, I2C. - sysreset driver - grf syscon driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Use rockchip_get_clk() to obtain the SoC clockSimon Glass2016-07-25-1/+1
| | | | | | | | | | | | The current code picks the first available clock. In U-Boot proper this is the oscillator device, not the SoC clock device. As a result the HDMI display does not work. Fix this by calling rockchip_get_clk() instead. Fixes: 135aa950 (clk: convert API to match reset/mailbox style) Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* rockchip: rk3288: fix FREF_MIN_HZ constantHeiko Stübner2016-07-25-1/+1
| | | | | | | | According to the TRM the minimum FREF frequency is 269kHz not MHz. Adapt the constant accordingly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* cosmetic: rockchip: rk3288: rename rkclk_configure_cpuHeiko Stübner2016-07-25-1/+1
| | | | | | | | | | The function is very specific to the rk3288 in its arguments referencing the rk3288 cru and grf and every other rockchip soc has differing cru and grf registers. So make that function naming explicit. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: use (devm_)ioremap() instead of map_sysmem()Masahiro Yamada2016-07-24-16/+7
| | | | | | | | This does not have much impact on behavior, but makes code look more more like Linux. The use of devm_ioremap() often helps to delete .remove callbacks entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* dm: clk: Remove simple version of clk_get_by_index/name()Michal Simek2016-07-22-27/+1
| | | | | | | | | | | | | | | | Simple version of clk_get_by_index() added by: "dm: clk: Add a simple version of clk_get_by_index()" (sha1: a4b10c088c4f6ef2e2bba33e8cfea369bcbbce44) is only working for #clock-cells=<1> but not for any other values. Fixed clocks is using #clock-cells=<0> which requires full implementation. Remove simplified versions of clk_get_by_index() and use full version. Also remove empty clk_get_by_name() which is failing when it is called which is useless. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* rockchip: clk: Update the rk3288 driver to support of-platdataSimon Glass2016-07-14-2/+18
| | | | | | | | Add support for of-platdata with rk3288. This requires decoding the of-platdata struct and setting up the devices from that. Also the driver needs to be renamed to match the string that of-platdata will search for. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: clk: Move all DT decoding to ofdata_to_platdata()Simon Glass2016-07-14-1/+12
| | | | | | | | It is more correct to avoid touching the device tree in the probe() method. Update the driver to work this way. Also add an error check on grf since if that fails then we should not use it. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: clk: Add support for of-platdataSimon Glass2016-07-14-2/+22
| | | | | | Add support for this feature in the core clock code. Signed-off-by: Simon Glass <sjg@chromium.org>
* clk: sandbox: don't check clk ID against 0Stephen Warren2016-06-24-4/+4
| | | | | | | | | | | | | clk->id is unsigned, so it can't be < 0. Remove the check for that. FWIW, this issue was introduced when the clock API converted e.g. clk_get_rate()'s clock ID parameter from an int to an unsigned long (with a struct clk), without removing this check. Fixes: 135aa9500264 ("clk: convert API to match reset/mailbox style") Reported-by: Coverity Scan Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* clk: convert API to match reset/mailbox styleStephen Warren2016-06-19-333/+396
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge http://git.denx.de/u-boot-samsungTom Rini2016-06-06-0/+307
|\ | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/peach-pi_defconfig configs/peach-pit_defconfig
| * clk: exynos: add clock driver for Exynos7420 SocThomas Abraham2016-05-25-0/+307
| | | | | | | | | | | | | | | | | | | | | | | | Add a clock driver for Exynos7420 SoC. There are about 25 clock controller blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks are added in this initial version of the driver. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-05-27-2/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For odroid-c2 (arch-meson) for now disable designware eth as meson now needs to do some harder GPIO work. Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: lib/efi_loader/efi_disk.c Modified: configs/odroid-c2_defconfig
| * | Rename reset to sysresetStephen Warren2016-05-26-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current reset API implements a method to reset the entire system. In the near future, I'd like to introduce code that implements the device tree reset bindings; i.e. the equivalent of the Linux kernel's reset API. This controls resets to individual HW blocks or external chips with reset signals. It doesn't make sense to merge the two APIs into one since they have different semantic purposes. Resolve the naming conflict by renaming the existing reset API to sysreset instead, so the new reset API can be called just reset. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | rockchip: rk3288: Add clock support for the gmac ethernet interfaceSjoerd Simons2016-05-27-0/+14
|/ / | | | | | | | | | | | | | | | | Setup the clocks for the gmac ethernet interface. This assumes the mac clock is fed by an external clock which is common on RK3288 based devices. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
* | clk: uniphier: add Media I/O clock driver support for PH1-LD11Masahiro Yamada2016-05-26-0/+4
|/ | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* clk: uniphier: add Media I/O clock driver support for PH1-LD20Masahiro Yamada2016-04-24-0/+4
| | | | | | PH1-LD20 needs this for its SD card controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* clk: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-6/+3
| | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* clk: uniphier: add Media I/O clock driver for UniPhier SoCsMasahiro Yamada2016-02-14-0/+413
| | | | | | | This is the initial commit for the UniPhier clock drivers. Currently, only the Media I/O clock is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-07-08 21:09:42 +0000