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path: root/drivers/block/ahci.c
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* ahci: Make ahci_port_base() non-static to enable overwriteStefan Roese2016-09-27-1/+1
| | | | | | | | | | | | | | | | To allow a board- / platform-specific ahci_port_base() function, this patch removes "static inline" and adds __weak to this function. This will be used by the upcoming Armada 7K/8K SATA / AHCI support, which unfortunately needs a different port base address calculation. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-23-1/+1
| | | | | | | | | | | Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
* ahci: flush dcache before issuing commandTang Yuantian2016-04-18-0/+1
| | | | | | | Ensure data the following sata command used is flushed out of dcache and written to physical memory or timeout error may happen. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
* dm: ahci: Convert to use new DM PCI APISimon Glass2016-01-12-7/+63
| | | | | | | Convert this driver to use the new driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Fix typo: firstly -> first.Vagrant Cascadian2015-12-05-2/+2
| | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Marek Vasut <marex@denx.de>
* Fix typo: commmand -> command.Vagrant Cascadian2015-12-05-2/+2
| | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* block: ahci: Remove dead codeFabio Estevam2015-11-12-36/+0
| | | | | | | | | CONFIG_AHCI_SETFEATURES_XFER is not selected by any user, so delete the dead code. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h headerSimon Glass2015-09-11-0/+1
| | | | | | | Now that we have a new header file for cache-aligned allocation, we should move the stack-based allocation macro there also. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-marvellTom Rini2015-07-10-3/+0
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| * block: ahci: Don't enable port interruptsStefan Roese2015-07-10-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the initialization of the AHCI controller to not enable the default interrupts (DEF_PORT_IRQ). As interrupts are not used in U-Boot in general, this should not break the common AHCI driver operation. This change is needed to support the Marvell Armada 38x AHCI controller. With interrupts enabled, this results in timeouts in ahci_device_data_io(). Not enabling these interrupts fixes this problem and the common AHCI driver works fine. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | ahci: Fix compiling warnings under 64bit platformsTang Yuantian2015-07-09-29/+35
|/ | | | | | | | | | | | | | | | | | | | When compling under 64bit platforms, there are lots of warnings, like: drivers/block/ahci.c:114:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; ^ drivers/block/ahci.c: In function ?.hci_host_init?. drivers/block/ahci.c:218:49: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); ...... Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
* ahci: extend data io wait to 10sMark Langsdorf2015-06-12-1/+1
| | | | | | | | | | | The AHCI driver currently waits 5s before timing out when sending a data command to a drive. Some drives take upwards of 8s to respond to the initial data command while they're spinning up. Increase the data io timeout to 10s so that those drives can be found on initial scsi scan. Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de>
* ahci: support LBA48 data reads for 2+TB drivesMark Langsdorf2015-06-12-9/+29
| | | | | | | | | | | | | | Enable full 48-bit LBA48 data reads by passing the upper word of the LBA block pointer in bytes 9 and 10 of the FIS. This allows uboot to load data from any arbitrary sector on a drive with 2 or more TB of available data connected to an AHCI controller. Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de> [trini: Make use of CONFIG_SYS_64BIT_LBA in a few places to drop warnings on platforms that don't enable that feature ] Signed-off-by: Tom Rini <trini@konsulko.com>
* ahci: mmio_base is a virtual addressScott Wood2015-04-18-5/+6
| | | | | | | | | | | | | | Don't store it in a u32. Don't dereference the bus address as if it were a virtual address (fixes 284231e49a2b4 ("ahci: Support splitting of read transactions into multiple chunks")). Fixes crash on boot in MPC8641HPCN_36BIT target. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Vadim Bendebury <vbendeb@chromium.org> Acked-by: York Sun <yorksun@freescale.com>
* ahci: Fix a wrong parameter passTang Yuantian2015-04-07-1/+1
| | | | | | | | | | | | In stead of user_buffer_size, transfer_size should be used to pass to ahci_device_data_io(). transfer_size is the length that we want the low level function to transfer each time. If we use user_buffer_size which is the totally data length as parameter, low level function will actually create many SGs to transfer as many data as possible each time. That will produce many redundant data transfer. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: ahci: Make sure interface is not busy after enabling the portBin Meng2015-01-23-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each time U-Boot boots on Intel Crown Bay board, the displayed hard drive information is wrong. It could be either wrong capacity or just a 'Capacity: not available' message. After enabling the debug switch, we can see the scsi inquiry command did not execute successfully. However, doing a 'scsi scan' in the U-Boot shell does not expose this issue. SCSI: Target spinup took 0 ms. SATA link 1 timeout. AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl SATA mode flags: ncq stag pm led clo only pmp pio slum part ccc apst scanning bus for devices... ahci_device_data_io: 0 byte transferred. <--- scsi inquiry fails ahci_device_data_io: 512 byte transferred. ahci_device_data_io: 512 byte transferred. ahci_device_data_io: 512 byte transferred. Device 0: (0:0) Vendor: ATA Prod.: Rev: ?8 Type: Hard Disk Capacity: 912968.3 MB = 891.5 GB (1869759264 x 512) Found 1 device(s). So uninitialized contents on the stack were passed to dev_print() to display those wrong information. The symptom were observed on two hard drives (one is Seagate, the other one is Western Digital). The fix is to make sure the AHCI interface is not busy by checking the error and status information from task file register after enabling the port in ahci_port_start() before proceeding other operations like scsi_scan(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ahci-plat: provide a weak scsi_bus_reset() hookDmitry Lifshitz2015-01-05-2/+1
| | | | | | | This allow the platform to handle a custom reset sequence. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
* ahci: introduce ahci_reset()Dmitry Lifshitz2015-01-05-17/+30
| | | | | | | | Extract controller reset code from ahci_host_init() into separate ahci_reset(). Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
* linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2014-11-23-1/+1
| | | | | | | | | | | | | | | | | | | | U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
* ahci: Don't start command DMA engine before buffers are setRoger Quadros2014-10-10-1/+0
| | | | | | | | | | | | The DMA/FIS buffers are set in ahci_port_start() which is called after ahci_host_init(). So don't start the DMA engine here (i.e. don't set FIS_RX) This fixes the following error at kernel boot on OMAP platforms (e.g. DRA7x) WARNING: CPU: 0 PID: 0 at drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x260/0x358() 44000000.ocp:L3 Custom Error: MASTER SATA TARGET GPMC (Idle): Data Access in User mode during Functional access Signed-off-by: Roger Quadros <rogerq@ti.com>
* ahci: provide sunxi SATA driver using AHCI platform frameworkIan Campbell2014-07-31-0/+16
| | | | | | | | | | | | | | | | | | | | | This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done for sun7i only since I don't have access to any other sunxi platforms with sata included. The PHY setup is derived from the Alwinner releases and Linux, but is mostly undocumented. The Allwinner AHCI controller also requires some magic (and, again, undocumented) DMA initialisation when starting a port. This is added under a suitable ifdef. This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on contents of Linux DTS files, including SATA power pin config taken from the DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* AHCI: Increase link timeout to 200msIan Campbell2014-07-22-1/+1
| | | | | | | | | | | | | In 73545f75b66d "ahci: wait longer for link" I increased the timeout to 40ms based on the observed behaviour of a WD disk on a Cubietruck. Since then Karsten Merker and myself have both observed timeouts with HGST disks (Karsten on Cubietruck, me on Cubieboard2). Increasing the timeout to ~175ms fixes this, so go to 200ms for a bit of headroom. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Karsten Merker <merker@debian.org> Acked-by: Hans de Goede <hdegoede@redhat.com>
* ahci: Fix data abort on multiple scsi resets.Roger Quadros2014-04-02-7/+16
| | | | | | | | | | | | | | | | | | | Commit 2faf5fb82ed6 introduced a regression that causes a data abort when running scsi init followed by scsi reset. There are 2 problems with the original commit 1) ALLOC_CACHE_ALIGN_BUFFER() allocates memory on the stack but is assigned to ataid[port] and used by other functions. 2) The function ata_scsiop_inquiry() tries to free memory which was never allocated on the heap. Fix these problems by using tmpid as a temporary cache aligned buffer. Allocate memory separately for ataid[port] and re-use it if required. Fixes: 2faf5fb82ed6 (ahci: Fix cache align error messages) Reported-by: Eli Nidam <elini@marvell.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
* ahci: wait longer for link.Ian Campbell2014-03-10-1/+1
| | | | | | | | | | | | I have observed timeouts on a cubietruck. The increase to 40ms is completely arbitrary and Works For Me(tm). I couldn't find a good reference for how long you are supposed to wait, although googling around it seems like tens of ms rather than single digits is more common. I don't think there is any harm in waiting a bit longer. Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
* ahci-plat: Provide a weak scsi_init hookIan Campbell2014-03-10-0/+5
| | | | | | This allow the platform to register the platform ahci device. Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
* ahci: Fix cache align error messagesRoger Quadros2013-12-04-7/+1
| | | | | | | | | | | | Align the ATA ID buffer to the cache-line boundary. This gets rid of the below error mesages on ARM v7 platforms. scanning bus for devices... ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xfee48818 CC: Aneesh V <aneesh@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
* ahci: Error out with message on malloc() failureRoger Quadros2013-12-04-2/+14
| | | | | | | | | If malloc() fails, we don't want to continue in ahci_init() and ahci_init_one(). Also print a more informative error message on malloc() failures. CC: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* ahci: convert to use libata functions and definitionsRob Herring2013-09-06-56/+24
| | | | | | | | | | | | | libata already has similar functions as implemented in the ahci code. Refactor the code to use the libata variants and remove the dependency on ata.h. Convert some defines to use the version from libata.h. Also, remove some unnecessary memset's of bss data. This is a step toward hopefully merging ahci.c and dw_ahsata.c which are essentially the same driver. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Tom Rini <trini@ti.com>
* ahci: increase spin-up timeout to 20 secRob Herring2013-09-06-1/+1
| | | | | | | | Based on Linux libata code, most drives are less than 10 sec, but some need up to 20 sec. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Tom Rini <trini@ti.com>
* ahci: handle COMINIT received during spin-upRob Herring2013-09-06-0/+12
| | | | | | | Some Intel SSDs can send a COMINIT after the initial COMRESET. This causes the link to go down and we need to re-initialize the link. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* ahci: move link bring-up handling to separate functionRob Herring2013-09-06-15/+25
| | | | | | | | Move the link bring-up handling to a separate weak function in order to allow platforms to override it. This is needed on highbank platform which needs special phy handling. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* ahci: add defines for PORT_SCR_STAT register bitsRob Herring2013-09-06-2/+3
| | | | | | | Replace hard-coded register values with proper defines for PORT_SCR_STAT register. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* ahci: fix memory leak in ata_scsiop_inquiryRob Herring2013-09-06-0/+1
| | | | | | | This fixes a memory leak when scsi inquiry fails. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Tom Rini <trini@ti.com>
* ahci: fix unaligned accessRob Herring2013-09-06-1/+1
| | | | | | | | gcc 4.7 will generate unaligned accesses to local char arrays, so make them static to avoid that. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Tom Rini <trini@ti.com>
* ahci: use ports implemented map instead of num_portsRichard Gibbs2013-09-06-0/+4
| | | | | | | | | The AHCI driver was incorrectly using the Capabilities register NP (number of ports) field to determine which ports to activate. This commit changes it to correctly use the PORTS_IMPL register as a port map. Signed-off-by: Richard Gibbs <richard.gibbs@calxeda.com> Reviewed-by: Tom Rini <trini@ti.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-18/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* Consolidate bool typeYork Sun2013-04-01-3/+3
| | | | | | | | | | | | | 'bool' is defined in random places. This patch consolidates them into a single header file include/linux/types.h, using stdbool.h introduced in C99. All other #define, typedef and enum are removed. They are all consistent with true = 1, false = 0. Replace FALSE, False with false. Replace TRUE, True with true. Skip *.py, *.php, lib/* files. Signed-off-by: York Sun <yorksun@freescale.com>
* ahci: Expand HDD Logical Block addressability up to 32 bitsWalter Murphy2012-11-02-4/+8
| | | | | | | | | | | | | | | | | | Currently, this driver uses a 28bit interface to AHCI, this limits the number of blocks addressable to 2^28, or the max disk size to 512(2^28) or about 137GB. This change allows supporting drives up to about 2TB. Testing this is a bit difficult. There is test code that can be inserted into U-Boot that will write test patterns into certain unused blocks. These patterns can be manually checked using 'dd' after boot. Another way is to confirm the original error that exposed this bug is fixed. IOW: see if AU (Auto Update) will now work on the drive. Also, check that there are no warning messages from the 'cgpt' utility. Signed-off-by: Walter Murphy <wmurphy@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* ahci: Perform SATA flush after disk write.Marc Jones2012-11-02-1/+51
| | | | | | | | | | Writes in u-boot are so rare, and the logic to know when is the last write and do a flush only there is sufficiently difficult. Just do a flush after every write. This incurs, usually, one extra flush when the rare writes do happen. Signed-off-by: Marc Jones <marc.jones@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* ahci: Support spin-up and link-up separatelyMarc Jones2012-11-02-6/+39
| | | | | | | | Add HDD handling to the SSD-only AHCI driver, by separately dealing with spin-up and link-up. Signed-off-by: Marc Jones <marc.jones@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* ahci: Adjust SATA timeouts for hard disk (spinup delay & command timeout)Walter Murphy2012-11-02-4/+10
| | | | | | | | | | | | | | | Note: These are timeout values and not delay values, so the event being timed out will complete whenever it is actually ready, with a measurement granularity of 1 millisecond, up till the timeout value. Therefore, there is no effect on SSD booting. The values were determined by instrumenting the code and measuring the actual time taken by several different models of HDD for each of the parameters and then adding 50% more for the spinup value and just doubling the command timeout value. Signed-off-by: Walter Murphy <wmurphy@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* ahci: flush / invalidate dcache around SATA commandsTaylor Hutt2012-11-02-0/+39
| | | | | | | | | Exynos5 automatically performs DMA when the SATA controller executes commands. This adds the necessary dcache-to-memory flush & invalidation calls to allow the DMA to properly function. Signed-off-by: Taylor Hutt <thutt@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* ahci: Use virt_to_phys() to denote physical addresses for DMATaylor Hutt2012-11-02-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Update the assignment of various physical memory buffers used by the SATA controller to explicitly be denoted as physical addresses. The memory is identity-mapped, so these function calls are a nop, but they provide good semantic documentation for any maintainers. The return value of virt_to_phys() is 'unsigned long'. On machines where sizeof(unsigned long) != sizeof(pointer), a cast through (uintptr_t) is needed to appease the compiler due to the potential of losing the upper 32 bits of the address. In compilation this scenario, a physical address could be 64-bits, yet the C pointer environment only allows 32-bit addresses; the constraint is that pointers cannot address more than 4Gb of memory and if virt_to_phys() ever returns an out-of-range value for the physical address, there are issues with emmory mapping which must be solved. However, since the memory is identify mappeed, there is no problem introducing the cast: the original pointer will reside in 32-bits, so the physical address will also be within in 32-bits. Signed-off-by: Taylor Hutt <thutt@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* ahci: Fix 'Invaild' typoTaylor Hutt2012-11-02-1/+1
| | | | | | | | This fixes a spelling error in a message which can be output to the console. Signed-off-by: Taylor Hutt <thutt@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* ahci: Use sizeof(fis) instead of hardcoding '20'Taylor Hutt2012-11-02-5/+5
| | | | | | | | This cleanup replaces the hardcoded use of '20', which represents the number of bytes in the FIS, with sizeof(fis). Signed-off-by: Taylor Hutt <thutt@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* ahci: Make the AHCI code find the capacity of disks > 128 GB properlyGabe Black2012-11-02-5/+50
| | | | | | | | | | | | | | | | | | | | | | | In the structure returned by the ATA identify device command, there are two fields which describe the device capacity. One is a 32 bit data type which reports the number of sectors as a 28 bit LBA, and the other is a 64 bit data type which is for a 48 bit LBA. If the device doesn't support 48 bit LBAs, the small value is the only value with the correct size. If it supports more, if the number of sectors is small enough to fit into 28 bits, both fields reflect the correct value. If it's too large, the smaller field has 28 bits of 1s, 0xfffffff, and the other field has the correct value. The AHCI driver is implemented by attaching to the generic SCSI code and translating on the fly between SCSI binary data structures and AHCI data structures. It responds to requests to execute specific SCSI commands by executing the equivalent AHCI commands and then crafting a response which matches what a SCSI disk would send. The AHCI driver now considers both fields and chooses the correct one when implementing both the SCSI READ CAPACITY (10) and READ CAPACITY (16) commands. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* ahci: support scsi writing in AHCI driverHung-Te Lin2012-11-02-24/+30
| | | | | | | | | | | | | | | | | | The "scsi write" command requires support from underlying driver. This CL enables SCSI_WRITE10 in AHCI driver. Tested in U-Boot console, try to i/o with sector #64: scsi read 1000 40 1 md.b 1000 200 # check if things are not 0xcc mw.b 1000 cc 200 # try to fill with 0xcc scsi write 1000 40 1 mw.b 1000 0 200 # fill with zero md.b 1000 200 # should be all 0 scsi read 1000 40 1 md.b 1000 200 # should be all 0xcc Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* ahci: Make sending the SETFEATURES_XFER command optionalGabe Black2012-11-02-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This command doesn't really do anything when talking to a SATA device, and sending it confuses some of them. This change makes sending the command optional, and defaults to not. The situations where it should be sent are not the common case. With the standard SSD in the machine, here are some times with the option turned off: 1. 8277 2. 8273 3. 8050 And turned on: 1. 8303 2. 8155 3. 8276 Sending that command seems to have no meaningful effect on performance. This fixes problems with an SSD marked Toshiba NV6424, Taiwan 11159AE P and TC58NVG5D2FTA10. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Taylor Hutt <thutt@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* ahci: cosmetics and cleanupStefan Reinauer2012-11-02-7/+18
| | | | | | | | | | | | | | | | - print the correct speed - print all the AHCI capability flags (information taken from Linux kernel driver) - clean up some comments For example, this might show the following string: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org>
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