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* spl: add USB Gadget config optionStefan Agner2016-11-28-3/+2
| | | | | | | | | Introduce USB Gadget config option. This allows to combine Makefile entries for SPL_USBETH_SUPPORT and SPL_DFU_SUPPORT. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Ravi Babu <ravibabu@ti.com>
* spl: dfu: move DFU Kconfig to SPL KconfigStefan Agner2016-11-28-0/+3
| | | | | | | | | | | | | | | | The DFU Kconfig menu entries should be part of the SPL Kconfig file. Also avoid using the top level Makefile by moving the config dependent build artifacts to the driver/ and driver/usb/gadget/ Makfiles. With that, DFU can be built again in SPL if CONFIG_SPL_DFU_SUPPORT is enabled. Fixes: 6ad6102246d8 ("usb:gadget: Disallow DFU in SPL for now") Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
* drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 3kStefan Roese2016-09-27-0/+1
| | | | | | | | | | | | | | | | | | This version is based on the Marvell U-Boot version with this patch applied as latest patch: Git ID 7f408573: "fix: comphy: cp110: add comphy initialization for usb device mode" from 2016-07-05. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
* Use separate options for TPL supportSimon Glass2016-09-16-1/+15
| | | | | | | | | | | | | | | At present TPL uses the same options as SPL support. In a few cases the board config enables or disables the SPL options depending on whether CONFIG_TPL_BUILD is defined. With the move to Kconfig, options are determined for the whole build and (without a hack like an #undef in a header file) cannot be controlled in this way. Create new TPL options for these and update users. This will allow Kconfig conversion to proceed for these boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* drivers/sysreset: group sysreset driversMax Filippov2016-08-12-1/+2
| | | | | | | | Create drivers/sysreset and move sysreset-uclass and all sysreset drivers there. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* spl: Lightweight UBI and UBI fastmap supportThomas Gleixner2016-07-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting a payload out of NAND FLASH from the SPL is a crux today, as it requires hard partioned FLASH. Not a brilliant idea with the reliability of todays NAND FLASH chips. The upstream UBI + UBI fastmap implementation which is about to brought to u-boot is too heavy weight for SPLs as it provides way more functionality than needed for a SPL and does not even fit into the restricted SPL areas which are loaded from the SoC boot ROM. So this provides a fast and lightweight implementation of UBI scanning and UBI fastmap attach. The scan and logical to physical block mapping code is developed from scratch, while the fastmap implementation is lifted from the linux kernel source and stripped down to fit the SPL needs. The text foot print on the board which I used for development is: 6854 0 0 6854 1abd drivers/mtd/ubispl/built-in.o Attaching a NAND chip with 4096 physical eraseblocks (4 blocks are reserved for the SPL) takes: In full scan mode: 1172ms In fastmap mode: 95ms The code requires quite some storage. The largest and unknown part of it is the number of fastmap blocks to read. Therefor the data structure is not put into the BSS. The code requires a pointer to free memory handed in which is initialized by the UBI attach code itself. See doc/README.ubispl for further information on how to use it. This shares the ubi-media.h and crc32 implementation of drivers/mtd/ubi There is no way to share the fastmap code, as UBISPL only utilizes the slightly modified functions ubi_attach_fastmap() and ubi_scan_fastmap() from the original kernel ubi fastmap implementation. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* mtd: Sort subsystem directories aplhabeticaly in MakefileLadislav Michl2016-07-22-2/+2
| | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* Add a reset driver framework/uclassStephen Warren2016-06-19-0/+1
| | | | | | | | | | | | | | | | A reset controller is a hardware module that controls reset signals that affect other hardware modules or chips. This patch defines a standard API that connects reset clients (i.e. the drivers for devices affected by reset signals) to drivers for reset controllers/providers. Initially, DT is the only supported method for connecting the two. The DT binding specification (reset.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/reset/reset.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* verified-boot: Minimal support for booting U-Boot proper from SPLTeddy Reed2016-06-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This allows a board to configure verified boot within the SPL using a FIT or FIT with external data. It also allows the SPL to perform signature verification without needing relocation. The board configuration will need to add the following feature defines: CONFIG_SPL_CRYPTO_SUPPORT CONFIG_SPL_HASH_SUPPORT CONFIG_SPL_SHA256 In this example, SHA256 is the only selected hashing algorithm. And the following booleans: CONFIG_SPL=y CONFIG_SPL_DM=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_OF_LIBFDT=y CONFIG_SPL_FIT_SIGNATURE=y Signed-off-by: Teddy Reed <teddy.reed@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Dannenberg <dannenberg@ti.com> Acked-by: Sumit Garg <sumit.garg@nxp.com>
* Add a mailbox driver framework/uclassStephen Warren2016-05-26-0/+1
| | | | | | | | | | | | | | | | A mailbox is a hardware mechanism for transferring small message and/or notifications between the CPU on which U-Boot runs and some other device such as an auxilliary CPU running firmware or a hardware module. This patch defines a standard API that connects mailbox clients to mailbox providers (drivers). Initially, DT is the only supported method for connecting the two. The DT binding specification (mailbox.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: mmc: spl: Use the legacy block interface in SPLSimon Glass2016-05-17-0/+1
| | | | | | | Bring this in for SPL so that we can use generic code for loading from block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: usb: Drop the get_dev() functionSimon Glass2016-05-17-0/+1
| | | | | | This function is implemented by the legacy block functions now. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* drivers: Add SPMI bus uclassMateusz Kulikowski2016-04-01-0/+1
| | | | | | | | | | | | Qualcom processors use proprietary bus to talk with PMIC devices - SPMI (System Power Management Interface). On wiring level it is similar to I2C, but on protocol level, it's multi-master and has simple autodetection capabilities. This commit adds simple uclass that provides bus read/write interface. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+1
| | | | | | | | | | | This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: Expand the uclass for Platform Controller Hubs (PCH)Simon Glass2016-01-24-0/+1
| | | | | | | | | | | | | | A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: mvebu: Move SoC selection (A38X vs AXP) into KconfigStefan Roese2016-01-14-2/+2
| | | | | | | | | | | | | | | | | | Until now, the SoC selection for the ARCH_MVEBU platforms has been done in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As it needed to get selected for AXP and A38x based boards. This patch now changes this to move the SoC selection to Kconfig. And also uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x. This makes things a bit clearer - especially for new board additions. Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available CONFIG_ARMADA_38X and CONFIG_ARMADA_XP. And CONFIG_DDR3 is removed, as its not referenced anywhere. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* Various Makefiles: Add SPDX-License-Identifier tagsTom Rini2015-11-10-0/+4
| | | | | | | | | | | After consulting with some of the SPDX team, the conclusion is that Makefiles are worth adding SPDX-License-Identifier tags too, and most of ours have one. This adds tags to ones that lack them and converts a few that had full (or in one case, very partial) license blobs into the equivalent tag. Cc: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* dm: adc: add simple ADC uclass implementationPrzemyslaw Marczak2015-11-02-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds: - new uclass id: UCLASS_ADC - new uclass driver: drivers/adc/adc-uclass.c The new uclass's API allows for ADC operation on: * single-channel with channel selection by a number * multti-channel with channel selection by bit mask ADC uclass's functions: * single-channel: - adc_start_channel() - start channel conversion - adc_channel_data() - get conversion data - adc_channel_single_shot() - start/get conversion data * multi-channel: - adc_start_channels() - start selected channels conversion - adc_channels_data() - get conversion data - adc_channels_single_shot() - start/get conversion data for channels selected by bit mask * general: - adc_stop() - stop the conversion - adc_vdd_value() - positive reference Voltage value with polarity [uV] - adc_vss_value() - negative reference Voltage value with polarity [uV] - adc_data_mask() - conversion data bit mask The device tree can provide below constraints/properties: - vdd-polarity-negative: if true: Vdd = vdd-microvolts * (-1) - vss-polarity-negative: if true: Vss = vss-microvolts * (-1) - vdd-supply: phandle to Vdd regulator's node - vss-supply: phandle to Vss regulator's node And optional, checked only if the above corresponding, doesn't exist: - vdd-microvolts: positive reference Voltage [uV] - vss-microvolts: negative reference Voltage [uV] Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* dm: implement a Timer uclassThomas Chou2015-10-23-0/+1
| | | | | | | Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
* drivers: Introduce a simplified remoteproc frameworkNishanth Menon2015-10-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many System on Chip(SoC) solutions are complex with multiple processors on the same die dedicated to either general purpose of specialized functions. Many examples do exist in today's SoCs from various vendors. Typical examples are micro controllers such as an ARM M3/M0 doing a offload of specific function such as event integration or power management or controlling camera etc. Traditionally, the responsibility of loading up such a processor with a firmware and communication has been with a High Level Operating System(HLOS) such as Linux. However, there exists classes of products where Linux would need to expect services from such a processor or the delay of Linux and operating system being able to load up such a firmware is unacceptable. To address these needs, we need some minimal capability to load such a system and ensure it is started prior to an Operating System(Linux or any other) is started up. NOTE: This is NOT meant to be a solve-all solution, instead, it tries to address certain class of SoCs and products that need such a solution. A very simple model is introduced here as part of the initial support that supports microcontrollers with internal memory (no MMU, no execution from external memory, or specific image format needs). This basic framework can then (hopefully) be extensible to other complex SoC processor support as need be. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
* pinctrl: add pin control uclass supportMasahiro Yamada2015-08-31-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This creates a new framework for handling of pin control devices, i.e. devices that control different aspects of package pins. This uclass handles pinmuxing and pin configuration; pinmuxing controls switching among silicon blocks that share certain physical pins, pin configuration handles electronic properties such as pin- biasing, load capacitance etc. This framework can support the same device tree bindings, but if you do not need full interface support, you can disable some features to reduce memory foot print. Typically around 1.5KB is necessary to include full-featured uclass support on ARM board (CONFIG_PINCTRL + CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX), for example. We are often limited on code size for SPL. Besides, we still have many boards that do not support device tree configuration. The full pinctrl, which requires OF_CONTROL, does not make sense for those boards. So, this framework also has a Do-It-Yourself (let's say simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the uclass itself provides no systematic mechanism for identifying the peripheral device, applying pinctrl settings, etc. They must be done in each low-level driver. In return, you can save much memory footprint and it might be useful especially for SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* led: unify obj-$(CONFIG_LED) and obj-$(CONFIG_SPL_LED) entriesMasahiro Yamada2015-08-18-2/+1
| | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* led: rename CONFIG_SPL_LED_SUPPORT to CONFIG_SPL_LEDMasahiro Yamada2015-08-18-1/+1
| | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ram: unify obj-$(CONFIG_RAM) and obj-$(CONFIG_SPL_RAM) entriesMasahiro Yamada2015-08-18-2/+1
| | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ram: rename CONFIG_SPL_RAM_SUPPORT to CONFIG_SPL_RAMMasahiro Yamada2015-08-18-1/+1
| | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: unify obj-$(CONFIG_CLK) and obj-$(CONFIG_SPL_CLK) entriesMasahiro Yamada2015-08-18-2/+1
| | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: rename CONFIG_SPL_CLK_SUPPORT to CONFIG_SPL_CLKMasahiro Yamada2015-08-18-1/+1
| | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: unify obj-$(CONFIG_DM) and obj-$(CONFIG_SPL_DM) entriesMasahiro Yamada2015-08-18-2/+2
| | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* spl: move SPL driver entries to driver/MakefileMasahiro Yamada2015-08-18-0/+37
| | | | | | | | | | | | | Just preparing for upcoming cleaning. The board-specific linker script board/vpac270/u-boot-spl.lds has been touched to avoid build error. It does not change the size of spl/u-boot-spl.bin for this board, so it should be OK. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: Add a clock uclassSimon Glass2015-07-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Add support for RAM driversSimon Glass2015-07-21-0/+1
| | | | | | | | Add support for a driver which sets up DRAM and can return information about the amount of RAM available. This is a first step towards moving RAM init to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Add support for LEDsSimon Glass2015-07-21-0/+1
| | | | | | | | | Add a simple uclass for LEDs, so that these can be controlled by the device tree and activated when needed. LEDs are referred to by their label. This implementation requires a driver for each type of LED (e.g GPIO, I2C). Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Implement a CPU uclassSimon Glass2015-04-29-0/+1
| | | | | | | | | | It is useful to be able to keep track of the available CPUs in a multi-CPU system. This uclass is mostly intended for use with SMP systems. The uclass provides methods for getting basic information about each CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-11-26-0/+1
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| * qe: add u-qe support to arm boardZhao Qiang2014-11-19-0/+1
| | | | | | | | | | | | | | | | | | ls1021 is arm-core and support qe which is u-qe. add u-qe init for arm board. Signed-off-by: Zhao Qiang <B45475@freescale.com> [York Sun: Fix compiling error caused by u_qe_init()] Reviewed-by: York Sun <yorksun@freescale.com>
* | DM: thermal: Add imx thermal DM driverYe.Li2014-11-21-0/+1
|/ | | | | | | | Add a new thermal uclass for thermal sensor and implement the imx thermal driver basing on this uclass. Signed-off-by: Ye.Li <B37916@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* soc: keystone_serdes: create a separate SGMII SerDes driverKhoronzhuk, Ivan2014-10-23-0/+2
| | | | | | | | | | | | | This patch split the Keystone II SGMII SerDes related code from Ethernet driver and create a separate SGMII SerDes driver. The SerDes driver can be used by others keystone subsystems like PCI, sRIO, so move it to driver/soc/keystone directory. Add soc specific drivers directory like in the Linux kernel. It is going to be used by keysotone soc specific drivers. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* kbuild: refactor some makefilesMasahiro Yamada2014-09-24-0/+3
| | | | | | | | | | | | | | | | | | [1] Move driver/core/, driver/input/ and drivers/input/ entries from the top Makefile to drivers/Makefile [2] Remove the conditional by CONFIG_DM in drivers/core/Makefile because the whole drivers/core directory is already selected by CONFIG_DM in the upper level [3] Likewise for CONFIG_DM_DEMO in drivers/demo/Makefile [4] Simplify common/Makefile - both CONFIG_DDR_SPD and CONFIG_SPD_EEPROM are boolean macros so they can directly select objects Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
* pwm, imx6: add support for pwm modul on imx6Heiko Schocher2014-07-23-0/+1
| | | | | | | | | | add basic support for the pwm modul found on imx6. Pieces of this code are based on linux code from drivers/pwm/pwm-imx.c Commit "cd3de83f1476 Linux 3.16-rc4" Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* ARM: keystone: aemif: move aemif driver to drivers/memory/ti-aemif.cKhoronzhuk, Ivan2014-06-19-0/+1
| | | | | | | | Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* drivers/qe: move the entry to drivers/MakefileMasahiro Yamada2013-11-17-0/+1
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* drivers: descend into sub directories only when it is necessaryMasahiro Yamada2013-11-17-2/+2
| | | | | | | - Descend into drivers/fpga/ only when CONFIG_FPGA=y - Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=y Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* drivers: move some drivers to drivers/MakefileMasahiro Yamada2013-10-31-0/+15
| | | | | | | | This commit moves some drivers subdirectory entry from the toplevel Makefile to drivers/Makefile using Kbuild descending feature. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* drivers/mtd : move mtd drivers to drivers/mtdJean-Christophe PLAGNIOL-VILLARD2007-11-25-54/+0
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* drivers/misc : move misc drivers to drivers/miscJean-Christophe PLAGNIOL-VILLARD2007-11-25-11/+0
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* drivers/block : move block drivers to drivers/blockJean-Christophe PLAGNIOL-VILLARD2007-11-25-5/+0
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* drivers/hwmon : move hardware monitor drviers to drivers/hwmonJean-Christophe PLAGNIOL-VILLARD2007-11-25-1/+0
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* drivers/input : move input drivers to drivers/inputJean-Christophe PLAGNIOL-VILLARD2007-11-25-9/+0
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* drivers/usb : move usb drivers to drivers/usbJean-Christophe PLAGNIOL-VILLARD2007-11-25-11/+0
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* drivers/serial : move serial drivers to drivers/serialJean-Christophe PLAGNIOL-VILLARD2007-11-25-7/+0
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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