summaryrefslogtreecommitdiff
path: root/doc
Commit message (Collapse)AuthorAgeLines
* armv8: LS2080A: Consolidate LS2080A and LS2085AYork Sun2016-04-06-1/+1
| | | | | | | | | | | | LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* Add myself as Snapdragon and SPMI maintainerMateusz Kulikowski2016-04-01-0/+3
| | | | | | | | - Update MAINTAINERS - Update git-mailrc Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* gpio: Add support for Qualcomm PM8916 gpiosMateusz Kulikowski2016-04-01-0/+48
| | | | | | | | | | | This driver supports GPIOs present on PM8916 PMIC. There are 2 device drivers inside: - GPIO driver (4 "generic" GPIOs) - Keypad driver that presents itself as GPIO with 2 inputs (power and reset) Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* pmic: Add support for Qualcomm PM8916 PMICMateusz Kulikowski2016-04-01-0/+18
| | | | | | | | This PMIC is connected on SPMI bus so needs SPMI support enabled. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* drivers: spmi: Add support for Qualcomm SPMI bus driverMateusz Kulikowski2016-04-01-0/+26
| | | | | | | | Support SPMI arbiter on Qualcomm Snapdragon devices. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* spmi: Add sandbox test driverMateusz Kulikowski2016-04-01-0/+31
| | | | | | | | This patch adds emulated spmi bus controller with part of pm8916 pmic on it to sandbox and tests validating SPMI uclass. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ehci: Add support for Qualcomm EHCIMateusz Kulikowski2016-04-01-0/+10
| | | | | | | | | | This driver is able to reconfigure OTG controller into HOST mode. Board can add board-specific initialization as board_prepare_usb(). It requires USB_ULPI_VIEWPORT enabled in board configuration. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* mmc: Add support for Qualcomm SDHCI controllerMateusz Kulikowski2016-04-01-0/+25
| | | | | | | | | | | Add support for SD/eMMC controller present on some Qualcomm Snapdragon devices. This controller implements SDHCI 2.0 interface but requires vendor-specific initialization. Driver works in PIO mode as ADMA is not supported by U-Boot (yet). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* gpio: Add support for Qualcomm gpio controllerMateusz Kulikowski2016-04-01-0/+22
| | | | | | | | | | Add support for gpio controllers on Qualcomm Snapdragon devices. This devices are usually called Top Level Mode Multiplexing in Qualcomm documentation. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* serial: Add support for Qualcomm serial portMateusz Kulikowski2016-04-01-0/+6
| | | | | | | | | This driver works in "new" Data Mover UART mode, so will be compatible with modern Qualcomm chips only. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* doc: clarify openssl-based key and certificate generation processAndreas Dannenberg2016-04-01-4/+4
| | | | | | | | Add some basic clarification that the dev.key file generated by OpenSSL contains both the public and private key, and further highlight that the certificate generated here contains the public key only. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
* doc: fix file extension for flattened image tree blobAndreas Dannenberg2016-04-01-1/+1
| | | | | | | | Different sections in the document suggest flattened image tree blob files have a file name extension of .itb. Fix the list of file extensions to reflect that. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
* arm: clang: Update support slightlyTom Rini2016-04-01-8/+7
| | | | | | | | | | | - Move most of the flags required into LLVM_RELFLAGS to test at build time instead of requiring them to be passed in. - Update doc/README.clang to reflect this - Switch to rpi_2 as the example as it's closer to working out of the box than rpi is. Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Signed-off-by: Tom Rini <trini@konsulko.com>
* doc/README.clang: Document sandbox instructionsTom Rini2016-03-27-0/+4
| | | | | | | | It is possible to compile and run the sandbox target with clang currently, so document that as well. Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: uniphier: switch to raw U-Boot imageMasahiro Yamada2016-03-24-6/+16
| | | | | | | | | | | | | | | | | Now everything is done to load a raw U-Boot proper image instead of an mkimage-processed one (as far as I tested on NAND, eMMC, NOR). The SPL already knows the load address of the U-Boot proper without parsing its uImage header because the load address is defined by CONFIG_SYS_TEXT_BASE, assuming that the two images are generated from the same build. My main motivation of this switch is to use u-boot-with-spl.bin, a concatenation of u-boot-spl.bin and u-boot.bin. (I wish there were a concatenation of u-boot-spl.bin and u-boot.img...) Anyway, this commit would be useful for one-shot image burn. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix README instruction for updating U-Boot via TFTPMasahiro Yamada2016-03-24-4/+4
| | | | | | | | | | Commit 3cb9abc9c512 ("ARM: uniphier: update U-Boot file names in workflow") missed to update these two sentences. Fix them now. Replace u-boot-spl-dtb.bin and u-boot-dtb.img with u-boot-spl.bin and u-boot.img, respectively. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Fix spelling of "transferred".Vagrant Cascadian2016-03-22-3/+3
| | | | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discreteShengzhou Liu2016-03-21-0/+9
| | | | | | | | | | Add support of address parity for DDR4 UDIMM or discrete memory. It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig, e.g. hwconfig=fsl_ddr:parity=on. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* x86: Add support for the samus chromebookSimon Glass2016-03-17-0/+81
| | | | | | | | | | | | | | | | | | | | | | | This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update README for new developmentsSimon Glass2016-03-17-3/+13
| | | | | | | Update a few points which have become out-of-date. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a pinctrl driverSimon Glass2016-03-17-0/+208
| | | | | | | | | | | GPIO pins need to be set up on start-up. Add a driver to provide this, configured from the device tree. The binding is slightly different from the existing ICH6 binding, since that is quite verbose. The new binding should be just as extensible. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: Update the pinctrl binding a littleSimon Glass2016-03-17-10/+11
| | | | | | | Make a few minor updates to make the meaning clearer. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an ICH6 pin configuration driverSimon Glass2016-03-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver which sets up the pin configuration on x86 devices with an ICH6 (or later) Platform Controller Hub. The driver is not in the pinctrl uclass due to some oddities of the way x86 devices work: - The GPIO controller is not present in I/O space until it is set up - This is done by writing a register in the PCH - The PCH has a driver which itself uses PCI, another driver - The pinctrl uclass requires that a pinctrl device be available before any other device can be probed It would be possible to work around the limitations by: - Hard-coding the GPIO address rather than reading it from the PCH - Using special x86 PCI access to set the GPIO address in the PCH However it is not clear that this is better, since the pin configuration driver does not actually provide normal pin configuration services - it simply sets up all the pins statically when probed. While this remains the case, it seems better to use a syscon uclass instead. This can be probed whenever it is needed, without any limitations. Also add an 'invert' property to support inverting the input. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a script to aid code conversion from corebootSimon Glass2016-03-17-0/+9
| | | | | | | | It is useful to automate the process of converting code from coreboot a little. Add a sed script which performs some common transformations. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Document how to play with SeaBIOSBin Meng2016-03-17-2/+55
| | | | | | | Boting SeaBIOS is done via U-Boot's bootelf command. Document this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* efi_loader: Add README section in README.efiAlexander Graf2016-03-15-1/+82
| | | | | | | | | | | | To preserve all cover letter knowledge of the status on UEFI payload support, let's add some sections to README.efi. Signed-off-by: Alexander Graf <agraf@suse.de> v3 -> v4: - Add section about config options - s/10kb/10KB/
* arm64: Remove non-full-va map codeAlexander Graf2016-03-15-20/+0
| | | | | | | | | | | By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-03-15-0/+77
|\
| * doc: dt-bindings: Describe rockchip LVDS interfaceJacob Chen2016-03-14-0/+77
| | | | | | | | | | | | | | | | I didn't have a common board to enable LVDS. So add this dcocument to help others who want to enable LVDS in their board. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Acked-by: Simon Glass <sjg@chromium.org>
* | mkimage: Support placing data outside the FITSimon Glass2016-03-14-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One limitation of FIT is that all the data is 'inline' within it, using a 'data' property in each image node. This means that to find out what is in the FIT it is necessary to scan the entire file. Once loaded it can be scanned and then the images can be copied to the correct place in memory. In SPL it can take a significant amount of time to copy images around in memory. Also loading data that does not end up being used is wasteful. It would be useful if the FIT were small, acting as a directory, with the actual data stored elsewhere. This allows SPL to load the entire FIT, without the images, then load the images it wants later. Add a -E option to mkimage to request that it output an 'external' FIT. Signed-off-by: Simon Glass <sjg@chromium.org>
* | mkimage: Support adding device tree files to a FITSimon Glass2016-03-14-0/+13
| | | | | | | | | | | | | | | | | | | | | | To make the auto-FIT feature useful we need to be able to provide a list of device tree files on the command line for mkimage to add into the FIT. Add support for this feature. So far there is no support for hashing or verified boot using this method. For those cases, a .its file must still be provided. Signed-off-by: Simon Glass <sjg@chromium.org>
* | mkimage: Support automatic creating of a FIT without a .itsSimon Glass2016-03-14-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present, when generating a FIT, mkimage requires a .its file containing the structure of the FIT and referring to the images to be included. Creating the .its file is a separate step that makes it harder to use FIT. This is not required for creating legacy images. Often the FIT is pretty standard, consisting of an OS image, some device tree files and a single configuration. We can handle this case automatically and avoid needing a .its file at all. To start with, support automatically generate the FIT using a new '-f auto' option. Initially this only supports adding a single image (e.g. a linux kernel) and a single configuration. Signed-off-by: Simon Glass <sjg@chromium.org>
* | tools: Add a function to obtain the size of a fileSimon Glass2016-03-14-2/+2
|/ | | | | | | This will be used in mkimage when working out the required size of the FIT based on the files to be placed into it. Signed-off-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: document how-to-build for Ace and Sanji boardsMasahiro Yamada2016-03-09-0/+8
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: merge two defconfig filesMasahiro Yamada2016-02-29-2/+2
| | | | | | | | PH1-Pro5 support and ProXstream2/PH1-LD6b support can coexist in one image and there is bit more room in SPL to accommodate all of them. Merge uniphier_pro5_defconfig into uniphier_pxs2_defconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add emmcupdate commandMasahiro Yamada2016-02-29-0/+14
| | | | | | | | | | | | The Boot ROM expects the boot image (SPL) in the Boot Partition 1. So, updating images involves the hardware partition switch. It might be a bit advanced for some users. To be user-friendly, this commit adds a useful command to update the images; just put SPL and U-Boot proper into the public directory of the TFTP server and execute "run emmcupdate" from the command line. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: uniphier: add driver for UniPhier SD/MMC host controllerMasahiro Yamada2016-02-29-0/+1
| | | | | | | Add a driver for the on-chip SD/eMMC host controller used by UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* gpio: uniphier: add driver for UniPhier GPIO controllerMasahiro Yamada2016-02-29-0/+1
| | | | | | | This GPIO controller device is used on UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: Remove ARM dcc from the listMichal Simek2016-02-24-1/+0
| | | | | | | Remove ARM Debug communication channel driver from the list of not converted drivers to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* x86: doc: Update to include Intel Bayley Bay board instructionsBin Meng2016-02-21-16/+20
| | | | | | | | | | | Update existing documentation to mention Intel Bayley Bay board instructions, an additional Bay Trail based board to MinnowMax. This also adds a minor change to QEMU section to indicate clearly the instructions are for bare mode. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Add Intel Cougar Canyon 2 boardBin Meng2016-02-21-0/+21
| | | | | | | | | This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Fix variable documented in README.distro for PXE address.Vagrant Cascadian2016-02-15-1/+1
| | | | | | | Fixes typo of pxe_addr_r with pxefile_addr_r. Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
* ARM: uniphier: update U-Boot file names in workflowMasahiro Yamada2016-02-14-3/+3
| | | | | | | | | | | | | | Since commit ad1ecd2063da ("fdt: Build a U-Boot binary without device tree") and commit 03c25bcd263a ("fdt: Build an SPL binary without device tree"), we can use shorter file names for the output images. The default configuration for UniPhier SoCs enables CONFIG_OF_SEPARATE and CONFIG_SPL_OF_CONTROL. In this case, spl/u-boot-spl.bin is the same as spl/u-boot-spl-dtb.bin. Likewise, u-boot.img is the same as as u-boot-dtb.img. So, this change of the flow has no impact. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* doc: Remove any reference to CONFIG_MODEM_SUPPORT, CONFIG_CMD_HWFLOW, ↵David Müller (ELSOFT AG)2016-02-08-72/+0
| | | | | | CONFIG_HWFLOW and friends from the documentation. Signed-off-by: David Müller <d.mueller@elsoft.ch>
* dm: Update on current serial driver statusSimon Glass2016-02-08-10/+4
| | | | | | Update the README to reflect the current status. Signed-off-by: Simon Glass <sjg@chromium.org>
* Use correct spelling of "U-Boot"Bin Meng2016-02-06-110/+110
| | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* mx6: soc: Add ENET2 mac address supportYe Li2016-02-02-1/+4
| | | | | | | The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading MAC address from fuse for ENET2. Signed-off-by: Ye Li <ye.li@nxp.com>
* drivers: serial: add driver for Microchip PIC32 UART controller.Paul Thacker2016-02-01-0/+5
| | | | | | | | | | This adds PIC32 UART controller support based on driver model. Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.Purna Chandra Mandal2016-02-01-0/+33
| | | | | | | | | | PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers and dividers capable of supplying clock to various controllers on or off-chip. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2016-01-29-0/+15
|\
generated by cgit v1.1 at 2024-11-01 17:54:40 +0000