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* Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-05-24-0/+25
|\ | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: drivers/net/zynq_gem.c
| * net: phy: dp83867: Add device tree bindings and documentationDan Murphy2016-05-24-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree bindings and the accompanying documentation for the TI DP83867 Giga bit ethernet phy driver. The original document was from: [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel] Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-05-23-0/+5
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| * x86: irq: Enable SCI on IRQ9Bin Meng2016-05-23-0/+5
| | | | | | | | | | | | | | | | | | | | By default SCI is disabled after power on. ACTL is the register to enable SCI and route it to PIC/APIC. To support both ACPI in PIC mode and APIC mode, configure SCI to use IRQ9. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* | drivers: spi: add spi support for QCA/Atheros ath79 SOCsWills Wang2016-05-21-0/+19
| | | | | | | | | | | | | | | | This patch add a compatible spi driver for ath79 series SOC. Signed-off-by: Wills Wang <wills.wang@live.com> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | drivers: serial: add serial driver for ar933x SOCWills Wang2016-05-21-0/+24
|/ | | | | | | | | This patch add support for ar933x serial. Signed-off-by: Wills Wang <wills.wang@live.com> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* i2c: Describe Cadence I2C devicetree bindingsMoritz Fischer2016-04-13-0/+20
| | | | | | Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* armv8: LS2080A: Consolidate LS2080A and LS2085AYork Sun2016-04-06-1/+1
| | | | | | | | | | | | LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* gpio: Add support for Qualcomm PM8916 gpiosMateusz Kulikowski2016-04-01-0/+48
| | | | | | | | | | | This driver supports GPIOs present on PM8916 PMIC. There are 2 device drivers inside: - GPIO driver (4 "generic" GPIOs) - Keypad driver that presents itself as GPIO with 2 inputs (power and reset) Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* pmic: Add support for Qualcomm PM8916 PMICMateusz Kulikowski2016-04-01-0/+18
| | | | | | | | This PMIC is connected on SPMI bus so needs SPMI support enabled. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* drivers: spmi: Add support for Qualcomm SPMI bus driverMateusz Kulikowski2016-04-01-0/+26
| | | | | | | | Support SPMI arbiter on Qualcomm Snapdragon devices. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* spmi: Add sandbox test driverMateusz Kulikowski2016-04-01-0/+31
| | | | | | | | This patch adds emulated spmi bus controller with part of pm8916 pmic on it to sandbox and tests validating SPMI uclass. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ehci: Add support for Qualcomm EHCIMateusz Kulikowski2016-04-01-0/+10
| | | | | | | | | | This driver is able to reconfigure OTG controller into HOST mode. Board can add board-specific initialization as board_prepare_usb(). It requires USB_ULPI_VIEWPORT enabled in board configuration. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* mmc: Add support for Qualcomm SDHCI controllerMateusz Kulikowski2016-04-01-0/+25
| | | | | | | | | | | Add support for SD/eMMC controller present on some Qualcomm Snapdragon devices. This controller implements SDHCI 2.0 interface but requires vendor-specific initialization. Driver works in PIO mode as ADMA is not supported by U-Boot (yet). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* gpio: Add support for Qualcomm gpio controllerMateusz Kulikowski2016-04-01-0/+22
| | | | | | | | | | Add support for gpio controllers on Qualcomm Snapdragon devices. This devices are usually called Top Level Mode Multiplexing in Qualcomm documentation. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* serial: Add support for Qualcomm serial portMateusz Kulikowski2016-04-01-0/+6
| | | | | | | | | This driver works in "new" Data Mover UART mode, so will be compatible with modern Qualcomm chips only. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* Fix spelling of "transferred".Vagrant Cascadian2016-03-22-1/+1
| | | | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* x86: broadwell: Add a pinctrl driverSimon Glass2016-03-17-0/+208
| | | | | | | | | | | GPIO pins need to be set up on start-up. Add a driver to provide this, configured from the device tree. The binding is slightly different from the existing ICH6 binding, since that is quite verbose. The new binding should be just as extensible. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: Update the pinctrl binding a littleSimon Glass2016-03-17-10/+11
| | | | | | | Make a few minor updates to make the meaning clearer. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an ICH6 pin configuration driverSimon Glass2016-03-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver which sets up the pin configuration on x86 devices with an ICH6 (or later) Platform Controller Hub. The driver is not in the pinctrl uclass due to some oddities of the way x86 devices work: - The GPIO controller is not present in I/O space until it is set up - This is done by writing a register in the PCH - The PCH has a driver which itself uses PCI, another driver - The pinctrl uclass requires that a pinctrl device be available before any other device can be probed It would be possible to work around the limitations by: - Hard-coding the GPIO address rather than reading it from the PCH - Using special x86 PCI access to set the GPIO address in the PCH However it is not clear that this is better, since the pin configuration driver does not actually provide normal pin configuration services - it simply sets up all the pins statically when probed. While this remains the case, it seems better to use a syscon uclass instead. This can be probed whenever it is needed, without any limitations. Also add an 'invert' property to support inverting the input. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* doc: dt-bindings: Describe rockchip LVDS interfaceJacob Chen2016-03-14-0/+77
| | | | | | | | I didn't have a common board to enable LVDS. So add this dcocument to help others who want to enable LVDS in their board. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Acked-by: Simon Glass <sjg@chromium.org>
* drivers: serial: add driver for Microchip PIC32 UART controller.Paul Thacker2016-02-01-0/+5
| | | | | | | | | | This adds PIC32 UART controller support based on driver model. Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.Purna Chandra Mandal2016-02-01-0/+33
| | | | | | | | | | PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers and dividers capable of supplying clock to various controllers on or off-chip. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-01-28-0/+229
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| * net: phy: micrel: add documentation for Micrel KSZ90x1 bindingDinh Nguyen2016-01-28-0/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the DTS documentation for the Micrel KSZ90x1 binding. The original document was from: [commit 4b405efbe12de28b26289282b431323d73992381 from the Linux kernel] This takes the original document and adds a clarification on how the skew values are represented in the code. References: Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014. http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014. http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: tsec: Use priv->tbiaddr to initialize TBI PHY addressBin Meng2016-01-28-0/+21
| | | | | | | | | | | | | | | | | | Add a new member 'tbiaddr' to tsec_private struct. For non-DM driver, it is initialized as CONFIG_SYS_TBIPA_VALUE, but for DM driver, we can get this from device tree. Update the bindings doc as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * doc: dt-bindings: Describe Freescale TSEC ethernet controllerBin Meng2016-01-28-0/+43
| | | | | | | | | | | | | | | | Adapted from the same file name in the kernel device tree bindings documentation, to use with U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-01-28-1/+30
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| * | x86: baytrail: Add documentation for FSP memory-down valuesStefan Roese2016-01-28-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the documentation for the memory-down parameters of the Intel FSP. To configure a board without SPD DDR DIMM but with onboard DDR chips. The values are taken from the coreboot header: src/soc/intel/fsp_baytrail/chip.h (git ID da1a70ea from 2016-01-16 as reference). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Andrew Bradford <andrew.bradford@kodakalaris.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | serial: uartlite: Move driver to DMMichal Simek2016-01-27-0/+13
|/ / | | | | | | | | | | | | Enable SPL DM too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
* | ns16550: replace with binding files from Linux kernelThomas Chou2016-01-25-10/+175
| | | | | | | | | | | | | | | | | | | | Replace ns16550.txt with binding files from Linux kernel. As suggested by Stephen Warren, we should keep the directory structure, filenames, and file content identical to the bindings in the Linux kernel. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | dts: Bring in pinctrl device tree bindingSimon Glass2016-01-21-0/+236
| | | | | | | | | | | | Add this binding file since we now use it in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: timer: uclass: add timer init in uclass driver to add timer deviceMugunthan V N2016-01-20-0/+43
|/ | | | | | | | | | Adding timer init function in timer-uclass driver to create and initialize the timer device on platforms where u-boot,dm-pre-reloc is not used. Since there will be multiple timer devices in the system, adding a tick-timer node in chosen node to know which timer device to be used as tick timer in u-boot. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* x86: Add an i8042 device for boards that have itSimon Glass2015-11-19-0/+10
| | | | | | | | | | | | Some boards have an i8042 device. Enable the driver for all x86 boards, and add a device tree node for those which may have this keyboard. Also adjust the configuration so that i8042 is always separate from the VGA, and rename the stdin driver accordingly. With this commit the keyboard will not work, but it is fixed in the next commit. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: add a sandbox timer and basic testThomas Chou2015-11-19-0/+7
| | | | | | | | Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* mtd: add altera quadspi driverThomas Chou2015-11-12-0/+35
| | | | | | | | Add Altera Generic Quad SPI Controller support. The controller converts SPI NOR flash to parallel flash interface. So it is not like other SPI flash, but rather like CFI flash. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* cfi_flash: convert to driver modelThomas Chou2015-11-12-0/+88
| | | | | | | Convert cfi flash to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: adc: add simple ADC uclass implementationPrzemyslaw Marczak2015-11-02-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds: - new uclass id: UCLASS_ADC - new uclass driver: drivers/adc/adc-uclass.c The new uclass's API allows for ADC operation on: * single-channel with channel selection by a number * multti-channel with channel selection by bit mask ADC uclass's functions: * single-channel: - adc_start_channel() - start channel conversion - adc_channel_data() - get conversion data - adc_channel_single_shot() - start/get conversion data * multi-channel: - adc_start_channels() - start selected channels conversion - adc_channels_data() - get conversion data - adc_channels_single_shot() - start/get conversion data for channels selected by bit mask * general: - adc_stop() - stop the conversion - adc_vdd_value() - positive reference Voltage value with polarity [uV] - adc_vss_value() - negative reference Voltage value with polarity [uV] - adc_data_mask() - conversion data bit mask The device tree can provide below constraints/properties: - vdd-polarity-negative: if true: Vdd = vdd-microvolts * (-1) - vss-polarity-negative: if true: Vss = vss-microvolts * (-1) - vdd-supply: phandle to Vdd regulator's node - vss-supply: phandle to Vss regulator's node And optional, checked only if the above corresponding, doesn't exist: - vdd-microvolts: positive reference Voltage [uV] - vss-microvolts: negative reference Voltage [uV] Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* dm: pmic: add s2mps11 PMIC I/O driverPrzemyslaw Marczak2015-11-02-0/+17
| | | | | | | | | | | | | | | | | | This driver allows I/O operations on the Samsung S2MPS11 PMIC, which provides lots of LDO/BUCK outputs. To enable it, update defconfig with: - CONFIG_PMIC_S2MPS11 and additional, if were not defined: - CONFIG_CMD_PMIC - CONFIG_ERRNO_STR The binding info: doc/device-tree-bindings/pmic/s2mps11.txt Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* s5p: cpu_info: print "cpu-model" if exists in dtsPrzemyslaw Marczak2015-11-02-0/+21
| | | | | | | | | | | | | | | | | | | | The CPU name for Exynos was concatenated with cpu id, but for new Exynos platforms, like Chromebook Peach Pi based on Exynos5800, the name of SoC variant does not include the real SoC cpu id (0x5422). For such case, the CPU name should be defined in device tree. This commit introduces new device-tree property for Exynos: - "cpu-model" - with cpu name string If defined, then the cpu id is not printed. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* doc: device-tree-bindings: spi: Add zynq qspi infoJagan Teki2015-10-25-0/+26
| | | | | | | | | | | Added device-tree-binding information for zynq qspi controller driver. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* net: convert altera_tse to driver model and phylibThomas Chou2015-10-23-0/+112
| | | | | | | | Convert altera_tse to driver model and phylib. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* nios2: convert altera sysid to driver modelThomas Chou2015-10-23-0/+4
| | | | | | | | Convert altera sysid to driver model with misc uclass. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* nios2: convert altera timer to driver modelThomas Chou2015-10-23-0/+19
| | | | | | | Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>
* nios2: convert nios2 cpu to driver modelThomas Chou2015-10-23-0/+54
| | | | | | | | | Convert nios2 cpu to driver model. The cpu parameters are extracted from device tree and saved to global data structure. We will use them to replace the custom_fpga.h . Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* nios2 : convert altera_pio to driver modelThomas Chou2015-10-23-0/+28
| | | | | | | | Convert altera_pio to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* spi : convert altera_spi to driver modelThomas Chou2015-10-23-0/+4
| | | | | | | Convert altera_spi to driver model Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Jagan Teki <jteki@openedev.com>
* nios2: convert altera_uart to driver modelThomas Chou2015-10-23-0/+7
| | | | | | | | Convert altera_uart to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* nios2: convert altera_jtag_uart to driver modelThomas Chou2015-10-23-0/+4
| | | | | | | | Convert altera_jtag_uart to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: Introduce a simplified remoteproc frameworkNishanth Menon2015-10-22-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many System on Chip(SoC) solutions are complex with multiple processors on the same die dedicated to either general purpose of specialized functions. Many examples do exist in today's SoCs from various vendors. Typical examples are micro controllers such as an ARM M3/M0 doing a offload of specific function such as event integration or power management or controlling camera etc. Traditionally, the responsibility of loading up such a processor with a firmware and communication has been with a High Level Operating System(HLOS) such as Linux. However, there exists classes of products where Linux would need to expect services from such a processor or the delay of Linux and operating system being able to load up such a firmware is unacceptable. To address these needs, we need some minimal capability to load such a system and ensure it is started prior to an Operating System(Linux or any other) is started up. NOTE: This is NOT meant to be a solve-all solution, instead, it tries to address certain class of SoCs and products that need such a solution. A very simple model is introduced here as part of the initial support that supports microcontrollers with internal memory (no MMU, no execution from external memory, or specific image format needs). This basic framework can then (hopefully) be extensible to other complex SoC processor support as need be. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
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