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* x86: baytrail: Add documentation for FSP memory-down valuesStefan Roese2016-01-28-1/+30
| | | | | | | | | | | | | | | | | This patch adds the documentation for the memory-down parameters of the Intel FSP. To configure a board without SPD DDR DIMM but with onboard DDR chips. The values are taken from the coreboot header: src/soc/intel/fsp_baytrail/chip.h (git ID da1a70ea from 2016-01-16 as reference). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Andrew Bradford <andrew.bradford@kodakalaris.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* ns16550: replace with binding files from Linux kernelThomas Chou2016-01-25-10/+175
| | | | | | | | | | Replace ns16550.txt with binding files from Linux kernel. As suggested by Stephen Warren, we should keep the directory structure, filenames, and file content identical to the bindings in the Linux kernel. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dts: Bring in pinctrl device tree bindingSimon Glass2016-01-21-0/+236
| | | | | | Add this binding file since we now use it in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: timer: uclass: add timer init in uclass driver to add timer deviceMugunthan V N2016-01-20-0/+43
| | | | | | | | | | Adding timer init function in timer-uclass driver to create and initialize the timer device on platforms where u-boot,dm-pre-reloc is not used. Since there will be multiple timer devices in the system, adding a tick-timer node in chosen node to know which timer device to be used as tick timer in u-boot. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* x86: Add an i8042 device for boards that have itSimon Glass2015-11-19-0/+10
| | | | | | | | | | | | Some boards have an i8042 device. Enable the driver for all x86 boards, and add a device tree node for those which may have this keyboard. Also adjust the configuration so that i8042 is always separate from the VGA, and rename the stdin driver accordingly. With this commit the keyboard will not work, but it is fixed in the next commit. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: add a sandbox timer and basic testThomas Chou2015-11-19-0/+7
| | | | | | | | Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* mtd: add altera quadspi driverThomas Chou2015-11-12-0/+35
| | | | | | | | Add Altera Generic Quad SPI Controller support. The controller converts SPI NOR flash to parallel flash interface. So it is not like other SPI flash, but rather like CFI flash. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* cfi_flash: convert to driver modelThomas Chou2015-11-12-0/+88
| | | | | | | Convert cfi flash to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: adc: add simple ADC uclass implementationPrzemyslaw Marczak2015-11-02-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds: - new uclass id: UCLASS_ADC - new uclass driver: drivers/adc/adc-uclass.c The new uclass's API allows for ADC operation on: * single-channel with channel selection by a number * multti-channel with channel selection by bit mask ADC uclass's functions: * single-channel: - adc_start_channel() - start channel conversion - adc_channel_data() - get conversion data - adc_channel_single_shot() - start/get conversion data * multi-channel: - adc_start_channels() - start selected channels conversion - adc_channels_data() - get conversion data - adc_channels_single_shot() - start/get conversion data for channels selected by bit mask * general: - adc_stop() - stop the conversion - adc_vdd_value() - positive reference Voltage value with polarity [uV] - adc_vss_value() - negative reference Voltage value with polarity [uV] - adc_data_mask() - conversion data bit mask The device tree can provide below constraints/properties: - vdd-polarity-negative: if true: Vdd = vdd-microvolts * (-1) - vss-polarity-negative: if true: Vss = vss-microvolts * (-1) - vdd-supply: phandle to Vdd regulator's node - vss-supply: phandle to Vss regulator's node And optional, checked only if the above corresponding, doesn't exist: - vdd-microvolts: positive reference Voltage [uV] - vss-microvolts: negative reference Voltage [uV] Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* dm: pmic: add s2mps11 PMIC I/O driverPrzemyslaw Marczak2015-11-02-0/+17
| | | | | | | | | | | | | | | | | | This driver allows I/O operations on the Samsung S2MPS11 PMIC, which provides lots of LDO/BUCK outputs. To enable it, update defconfig with: - CONFIG_PMIC_S2MPS11 and additional, if were not defined: - CONFIG_CMD_PMIC - CONFIG_ERRNO_STR The binding info: doc/device-tree-bindings/pmic/s2mps11.txt Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* s5p: cpu_info: print "cpu-model" if exists in dtsPrzemyslaw Marczak2015-11-02-0/+21
| | | | | | | | | | | | | | | | | | | | The CPU name for Exynos was concatenated with cpu id, but for new Exynos platforms, like Chromebook Peach Pi based on Exynos5800, the name of SoC variant does not include the real SoC cpu id (0x5422). For such case, the CPU name should be defined in device tree. This commit introduces new device-tree property for Exynos: - "cpu-model" - with cpu name string If defined, then the cpu id is not printed. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* doc: device-tree-bindings: spi: Add zynq qspi infoJagan Teki2015-10-25-0/+26
| | | | | | | | | | | Added device-tree-binding information for zynq qspi controller driver. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* net: convert altera_tse to driver model and phylibThomas Chou2015-10-23-0/+112
| | | | | | | | Convert altera_tse to driver model and phylib. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* nios2: convert altera sysid to driver modelThomas Chou2015-10-23-0/+4
| | | | | | | | Convert altera sysid to driver model with misc uclass. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* nios2: convert altera timer to driver modelThomas Chou2015-10-23-0/+19
| | | | | | | Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>
* nios2: convert nios2 cpu to driver modelThomas Chou2015-10-23-0/+54
| | | | | | | | | Convert nios2 cpu to driver model. The cpu parameters are extracted from device tree and saved to global data structure. We will use them to replace the custom_fpga.h . Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* nios2 : convert altera_pio to driver modelThomas Chou2015-10-23-0/+28
| | | | | | | | Convert altera_pio to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* spi : convert altera_spi to driver modelThomas Chou2015-10-23-0/+4
| | | | | | | Convert altera_spi to driver model Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Jagan Teki <jteki@openedev.com>
* nios2: convert altera_uart to driver modelThomas Chou2015-10-23-0/+7
| | | | | | | | Convert altera_uart to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* nios2: convert altera_jtag_uart to driver modelThomas Chou2015-10-23-0/+4
| | | | | | | | Convert altera_jtag_uart to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: Introduce a simplified remoteproc frameworkNishanth Menon2015-10-22-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many System on Chip(SoC) solutions are complex with multiple processors on the same die dedicated to either general purpose of specialized functions. Many examples do exist in today's SoCs from various vendors. Typical examples are micro controllers such as an ARM M3/M0 doing a offload of specific function such as event integration or power management or controlling camera etc. Traditionally, the responsibility of loading up such a processor with a firmware and communication has been with a High Level Operating System(HLOS) such as Linux. However, there exists classes of products where Linux would need to expect services from such a processor or the delay of Linux and operating system being able to load up such a firmware is unacceptable. To address these needs, we need some minimal capability to load such a system and ensure it is started prior to an Operating System(Linux or any other) is started up. NOTE: This is NOT meant to be a solve-all solution, instead, it tries to address certain class of SoCs and products that need such a solution. A very simple model is introduced here as part of the initial support that supports microcontrollers with internal memory (no MMU, no execution from external memory, or specific image format needs). This basic framework can then (hopefully) be extensible to other complex SoC processor support as need be. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Bring in RK3288 device tree file includes and bindingsSimon Glass2015-09-02-0/+579
| | | | | | | | Bring in required device tree files from Linux. Since mainline Linux is somewhat behind, use the files from the Chromium tree. We can re-sync once further code is acccepted upstream. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Configure FSP UPD from device treeAndrew Bradford2015-08-14-0/+158
| | | | | | | | | | | | | | | | | Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself. Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay Fixed lines >80col Signed-off-by: Simon Glass <sjg@chromium.org>
* power: regulator: update comments for regulator-namePeng Fan2015-08-12-11/+8
| | | | | | | | | | We do not need that "regulator-name" property must be provided in dts. If "regulator-name" property is not provided in dts, node name will chosen for settings '.name' field of uc_pdata. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org>
* dm: video: Add support for the Parade PS8622/625 bridgeSimon Glass2015-08-05-0/+33
| | | | | | | | This chip provides an eDP to LVDS bridge which is useful for SoCs that don't support LVDS displays (or it would waste scarce pins). The setup is included in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: i2c: Add support for multiplexed I2C busesSimon Glass2015-08-05-0/+60
| | | | | | | | | | | | | | | | | Add a new I2C_MUX uclass. Devices in this class can multiplex between several I2C buses, selecting them one at a time for use by the system. The multiplexing mechanism is left to the driver to decide - it may be controlled by GPIOs, for example. The uclass supports only two methods: select() and deselect(). The current mux state is expected to be stored in the mux itself since it is the only thing that knows how to make things work. The mux can record the current state and then avoid switching unless it is necessary. So select() can be skipped if the mux is already in the correct state. Also deselect() can be made a nop if required. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: dts: Fix typo in intel,irq-router.txtSimon Glass2015-08-05-2/+2
| | | | | | | Fix a small typo in this binding file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: Fix zynq SPI bindingMichal Simek2015-07-28-16/+19
| | | | | | | | Zynq is using Cadence IP where binding is documented in the Linux kernel and there is no reason to use different binding. Synchronize it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* dm: led: Add a driver for GPIO-controlled LEDsSimon Glass2015-07-21-0/+52
| | | | | | | Add a simple driver which allows use of LEDs attached to GPIOs. The linux device tree binding is used. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Add support for LEDsSimon Glass2015-07-21-0/+23
| | | | | | | | | Add a simple uclass for LEDs, so that these can be controlled by the device tree and activated when needed. LEDs are referred to by their label. This implementation requires a driver for each type of LED (e.g GPIO, I2C). Signed-off-by: Simon Glass <sjg@chromium.org>
* spi: cadence_qspi: add device tree binding docVikas Manocha2015-07-03-0/+28
| | | | | | | | This patch adds the device tree binding doc for the cadence qspi controller & also removes the not needed properties from the stv0991 device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* spi: zynq_spi: Add fdt support in driverJagan Teki2015-07-01-0/+2
| | | | | | | | | | | | | | | | | Now zynq spi driver platform data is controlled by devicetree, enable the status by saying "okay" on respective board dts to use the devicetree generated platdata. Ex: &spi1 { status = "okay"; }; Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* dts: zynq: Add zynq spi controller nodesJagan Teki2015-07-01-0/+27
| | | | | | | | | | This patch adds zynq spi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* Merge git://git.denx.de/u-boot-fdtTom Rini2015-06-05-0/+4
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| * fdt: Pass the device serial number through devicetreePaul Kocialkowski2015-06-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before device-tree, the device serial number used to be passed to the kernel using ATAGs (on ARM). This is now deprecated and all the handover to the kernel should now be done using device-tree. Thus, this passes the serial-number property to the kernel using the serial-number property of the root node, as expected by the kernel. The serial number is a string that somewhat represents the device's serial number. It might come from some form of storage (e.g. an eeprom) and be programmed at factory-time by the manufacturer or come from identification bits available in e.g. the SoC. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Simon Glass <sgj@chromium.org>
* | x86: gpio: add pinctrl support from the device treeGabriel Huau2015-06-04-0/+31
| | | | | | | | | | | | | | | | | | Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Document irq router device tree bindingsBin Meng2015-06-04-0/+50
|/ | | | | | | Describe all required properties needed by the irq router device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* sandbox: add: sandbox PMIC device drivers: I2C emul, pmic, regulatorPrzemyslaw Marczak2015-05-14-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds emulation of sandbox PMIC device, which includes: - PMIC I2C emulation driver - PMIC I/O driver (UCLASS_PMIC) - PMIC regulator driver (UCLASS_REGULATOR) The sandbox PMIC has 12 significant registers and 4 as padding to 16 bytes, which allows using 'i2c md' command with the default count (16). The sandbox PMIC provides regulators: - 2x BUCK - 2x LDO Each, with adjustable output: - Enable state - Voltage - Current limit (LDO1/BUCK1 only) - Operation mode (different for BUCK and LDO) Each attribute has it's own register, beside the enable state, which depends on operation mode. The header file: sandbox_pmic.h includes PMIC's default register values, which are set on i2c pmic emul driver's probe() method. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on sandbox: Tested-by: Simon Glass <sjg@chromium.org>
* dm: regulator: add fixed voltage regulator driverPrzemyslaw Marczak2015-05-14-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | This driver implements regulator operations for fixed Voltage/Current value regulators. beside the standard regulator constraints, which are put into the uclass platform data, a typical fixed regulator node provides few additional properties like: - gpio - gpio-open-drain - enable-active-high - startup-delay-us The only 'gpio' is used by this driver and is kept in structure of type 'fixed_regulator_platdata', as a device platform data (dev->platdata). The driver implements: - get_value - get_current - get_enable - set_enable The regulator calls and commands can be used for fixed-regulator devices, and the proper error will be returned for prohibited. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: regulator: add max77686 regulator driverPrzemyslaw Marczak2015-05-14-0/+70
| | | | | | | | | | | | | | This commit adds support to MAX77686 regulator driver, based on a driver model regulator's API. It implements almost all regulator operations, beside those for setting and geting the Current value. For proper bind and operation it requires the MAX77686 PMIC driver. New file: drivers/power/regulator/max77686.c New config: CONFIG_DM_REGULATOR_MAX77686 Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pmic: add max77686 pmic driverPrzemyslaw Marczak2015-05-14-0/+35
| | | | | | | | | | | | | | | This is the implementation of driver model PMIC driver. The max77686 PMIC driver implements read/write operations and driver bind method - to bind its childs. This driver will try to bind the regulator devices by using it's child info array with regulator prefixes and driver names. This should succeed when compatible regulator driver is compiled. If no regulator driver found, then the pmic can still provide read/write operations, and can be used with PMIC function calls. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: regulator: add implementation of driver model regulator uclassPrzemyslaw Marczak2015-05-14-0/+54
| | | | | | | | | | | | | | | | | | This commit introduces the implementation of dm regulator API. Device tree support allows for auto binding. And by the basic uclass operations, it allows to driving the devices in a common way. For detailed informations, please look into the header file. Core files: - drivers/power/regulator-uclass.c - provides regulator common functions api - include/power/regulator.h - define all structures required by the regulator Changes: - new uclass-id: UCLASS_REGULATOR - new config: CONFIG_DM_REGULATOR Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* tegra124: dts: Add host1x node to provide display informationSimon Glass2015-05-13-0/+372
| | | | | | | | This peripheral is required to get the LCD display running. Add it to tegra124 and also bring in the binding file from Linux 3.18 Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* fdt: Add binding decode function for display-timingsSimon Glass2015-05-13-0/+110
| | | | | | | | This is useful for display parameters. Add a simple decode function to read from this device tree node. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* serial: fdt: add device tree support for pl01xVikas Manocha2015-05-10-0/+7
| | | | | | | This patch adds device tree support for arm pl010/pl011 driver. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Acked-by: Simon Glass <sjg@chromium.org>
* dts: sunxi: Bring in Ethernet device tree bindingsSimon Glass2015-04-18-0/+161
| | | | | | | | Since we will use these bindings on sunxi, bring them in from Linux 4.0-rc1. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* dm: i2c: add i2c-gpio driverPrzemyslaw Marczak2015-04-18-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds driver model support to software emulated i2c bus driver. This driver supports kernel-style device tree bindings. Fdt properties in use: - compatible - "i2c-gpio" - gpios - data and clock GPIO pin phandles - delay-us - micro seconds delay between GPIOs toggle operations, which is 1/4 of I2C speed clock period. Added: - Config: CONFIG_DM_I2C_GPIO - File: drivers/i2c/i2c-gpio.c - File: doc/device-tree-bindings/i2c/i2c-gpio.txt Driver base code is taken from: drivers/i2c/soft-i2c.c, changes: - use "i2c-gpio" naming - update comments style - move preprocesor macros into functions - add device tree support - add driver model i2c support - code cleanup, - add Kconfig entry Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Added braces in i2c_gpio_xfer() to fix style nit: Signed-off-by: Simon Glass <sjg@chromium.org>
* video: exynos_fb: configure backlight GPIOs if specified in DTAjay Kumar2015-04-06-0/+2
| | | | | | | | | | Add support to configure PWM_OUT(PWM output) GPIO and BL_EN(backlight enable) GPIO, if provided in FIMD DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Documentation: gpio: fix bindings documentMasahiro Yamada2015-02-19-2/+3
| | | | | | | | [ imported from Linux Kernel, commit 74981fb81d83 ] Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Simon Glass <sjg@chromium.org>
* samsung: board: support eMMC reset using DTJoonyoung Shim2015-02-13-0/+15
| | | | | | | | | | | Some exynos boards require special handling of nRESET_OUT line for eMMC memory to perform complete reboot e.g. Odroid X2/U3/XU3 boards. This will support eMMC reset using DT from reset_misc of samsung common board file. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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