summaryrefslogtreecommitdiff
path: root/doc/device-tree-bindings/misc/intel-lpc.txt
Commit message (Collapse)AuthorAgeLines
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-3/+44
| | | | | | | Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add early LPC init so that serial worksSimon Glass2014-11-21-0/+23
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>