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* x86: Mention running U-Boot in 64-bit mode in the READMESimon Glass2016-08-16-0/+18
| | | | | | | | This feature is not supported. Document this, and add some details on how it might be implemented. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a reference to README.efiSimon Glass2016-08-16-0/+11
| | | | | | | | UEFI is commonly used on x86. Add a reference to U-Boot's support for this in the x86 README. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: doc: Add note about the debug FSP usage on BayTrailStefan Roese2016-08-16-0/+4
| | | | | | | | | | | The debug FSP image is bigger in size than the normal FSP image. This patch adds a small description on how to use this FSP debug version by changing CONFIG_FSP_ADDR. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: acpi: Pack global NVS into ACPI tableBin Meng2016-07-12-2/+0
| | | | | | | | | | Now that platform-specific ACPI global NVS is added, pack it into ACPI table and get its address fixed up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: galileo: Enable ACPI table generationBin Meng2016-05-30-1/+4
| | | | | | | Enable ACPI table generation by creating a DSDT table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: doc: Add porting hints for ACPI with WindowsBin Meng2016-05-23-0/+6
| | | | | | | | Windows might cache system information and only detect ACPI changes if you modify the ACPI table versions. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: doc: Mention Ubuntu/Windows installation and boot supportBin Meng2016-05-23-4/+8
| | | | | | | | As of now, U-Boot can support installing and booting Ubuntu/Windows with the help of SeaBIOS. Update the documentation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: doc: Update information about IGD with SeaBIOSBin Meng2016-05-23-0/+24
| | | | | | | | Document how to make SeaBIOS load and run the VGA ROM of Intel IGD device when loaded by U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: Adjust U-Boot environment address in SPI flashBin Meng2016-05-23-1/+1
| | | | | | | | | | | | | | | Currently U-Boot environment address is at offset 0x7fe00 of a 8MB SPI flash. When creating a partial u-boot.rom image without flash descriptor and ME firmware, U-Boot actually occupies the last 1MB of the flash, and reprograming U-Boot causes previous environment settings get lost which is not convenient during testing. Adjust the environment address to 0x6ef000 instead (before the MRC cache data region in the flash). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: doc: Document ACPI supportBin Meng2016-05-23-1/+43
| | | | | | | | Remove ACPI from the TODO list and add a new section to document current ACPI support in U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: doc: Minor update for accuracyBin Meng2016-05-23-23/+18
| | | | | | | | | | | | | | | | This updates the doc for the following places: - Mention CRB for Bayley Bay - Mention Congatec QEVAL 2.0 & conga-QA3/E3845 - Limit part of the QEMU paragraphs to 80 cols - Correct some typos (drive, it's, Ubuntu) - Add description for "console=ttyS0,115200" - Remove CONFIG_BOOTDELAY description which is already in x86-common.h Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Add support for the samus chromebookSimon Glass2016-03-17-0/+81
| | | | | | | | | | | | | | | | | | | | | | | This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update README for new developmentsSimon Glass2016-03-17-3/+13
| | | | | | | Update a few points which have become out-of-date. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a script to aid code conversion from corebootSimon Glass2016-03-17-0/+9
| | | | | | | | It is useful to automate the process of converting code from coreboot a little. Add a sed script which performs some common transformations. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Document how to play with SeaBIOSBin Meng2016-03-17-2/+55
| | | | | | | Boting SeaBIOS is done via U-Boot's bootelf command. Document this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: doc: Update to include Intel Bayley Bay board instructionsBin Meng2016-02-21-16/+20
| | | | | | | | | | | Update existing documentation to mention Intel Bayley Bay board instructions, an additional Bay Trail based board to MinnowMax. This also adds a minor change to QEMU section to indicate clearly the instructions are for bare mode. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Add Intel Cougar Canyon 2 boardBin Meng2016-02-21-0/+21
| | | | | | | | | This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Add option to disable the internal UART to setup_early_uart()Stefan Roese2016-01-28-1/+1
| | | | | | | | | | | This patch adds a parameter to the function setup_early_uart() to either enable or disable the internal BayTrail legacy UART. Since the name setup_early_uart() does not match its functionality any more, lets rename it to setup_internal_uart() as well in this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: qemu: add documentaion for the fw_cfg interfaceMiao Yan2016-01-13-3/+31
| | | | | | | | Document the usage of 'qfw' command Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Enable mrc cache for bayleybay and minnowmaxBin Meng2015-10-21-0/+1
| | | | | | | | | | | | Now that we have added MRC cache for Intel FSP and BayTrail codes, enable it for all BayTrail boards (Bayley Bay and Minnow Max). Note it turns out that FSP for Intel Atom E6xx does not produce the HOB for NV storage, so we don't have such functionality on Intel Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Make hob command a sub-command to fspBin Meng2015-10-21-3/+2
| | | | | | | | | Introduce a new fsp command and make the existing hob command a sub-command to fsp for future extension. Also move cmd_hob.c to the dedicated fsp sub-directory in arch/x86/lib. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add SMBIOS table supportBin Meng2015-10-21-2/+0
| | | | | | | | | | | | System Management BIOS (SMBIOS) is a specification for how motherboard and system vendors present management information about their products in a standard format by extending the BIOS interface on Intel architecture systems. As of today the latest spec is 3.0 and can be downloaded from DMTF website. This commit adds a simple and minimum required implementation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* doc: Complement document about booting VxWorksBin Meng2015-10-21-0/+2
| | | | | | | | Current document about how to boot VxWorks is limited. Add several chapters in README.vxworks to document this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* x86: doc: Add DMI to the TODO listBin Meng2015-09-16-0/+2
| | | | | | | | Desktop Management Interface (DMI) is not supported by U-Boot now. Add it to the TODO list. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: doc: Document some porting hints about Intel QuarkBin Meng2015-09-16-0/+24
| | | | | | | | Document porting considerations for Intel Quark based board, including MRC parameters and PCIe initialization. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: doc: Change to use CONFIG_VGA_BIOS_ADDRBin Meng2015-09-09-1/+1
| | | | | | | | | CONFIG_X86_OPTION_ROM_ADDR has been renamed to CONFIG_VGA_BIOS_ADDR. Update the doc to refer to the new name. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Correct microcode documentationSimon Glass2015-08-26-2/+2
| | | | | | | | This is incorrect since we require the -m parameter to the microcode tool. Update the two examples to show this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: doc: Update coreboot payload entry point addressBin Meng2015-08-26-3/+3
| | | | | | | | With recent EFI support, the entry point address of coreboot payload was changed. Now we update the address to use _x86boot_start, which is the same one for EFI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a simple interrupt script to the READMESimon Glass2015-08-14-0/+15
| | | | | | | | | | It is a bit tedious to figure out the interrupt configuration for a new x86 platform. Add a script which can do this, based on the output of 'pci long'. This may be helpful in some cases. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add clarifications to the x86 READMEStoppa, Igor2015-08-14-11/+21
| | | | | | | | | | * Explicitly list the targets supported in each section of the instructions from the x86 README. * Drop references to 'raw mode', in favor of 'bare mode'. Signed-off-by: Igor Stoppa <igor.stoppa@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Document how to write PIRQ information in the device treeBin Meng2015-08-05-0/+41
| | | | | | | | Document the development flow on figuring out PIRQ information during the U-Boot porting. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Update README to explain booting Ubuntu on MinnowmaxSimon Glass2015-08-05-0/+278
| | | | | | | | | | | | | | | | The steps required to boot a Linux distribution from U-Boot on x86 are not very complicated, but it is a good idea to have these written down in an accessible place. Document how to examine the boot media from U-Boot, how to load a kernel, load a ramdisk, set the kernel boot arguments and start the kernel. With these instructions Ubuntu boots mostly normally on Minnowmax. Note that the TSC timer does not operate correctly and gives warnings in the boot log. I expect that ACPI support will solve this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: Add MP initializationBin Meng2015-08-05-0/+5
| | | | | | | | | Add a cpu1 node to the device tree and enable the MP initialization on QEMU targets (i440fx and q35). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Add binary blob checksums for Minnowboard MAXSimon Glass2015-07-14-0/+8
| | | | | | | | | | To try to reduce the pain of confusion of binary blobs, add MD5 checksums for the current versions. This may worsen the situation as new versions appear, but it should still be possible to obtain these versions, and thus get a working setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add ROM image description for minnowmaxSimon Glass2015-07-14-0/+17
| | | | | | | | The layout of the ROM is a bit hard to discover by reading the code. Add a table to make it easier. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: crownbay: Enable graphics supportBin Meng2015-07-14-7/+13
| | | | | | | | | | | Enable graphics support on Intel Crown Bay board With the help of vgabios for Intel TunnelCreek IGD. Tested with an external LVDS panel connected to X4 connector and SDVO adapter connected to X9 connector on the board. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move VGA option rom macros to KconfigBin Meng2015-07-14-1/+1
| | | | | | | | | | Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Update README.x86 for SMP supportBin Meng2015-07-14-0/+13
| | | | | | | | Document U-Boot multi-processor support as well as configuration tables like SFI and MP tables for SMP OS kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Create separate i440fx and q35 device treesBin Meng2015-06-04-1/+9
| | | | | | | | | | Although the two qemu-x86 targets (i440fx and q35) share a lot in common, they still have something that cannot easily handled in one single device tree). Split to create two dedicated device tree files and make the i440fx be the default build target. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Add graphics supportBin Meng2015-06-04-1/+6
| | | | | | | | It turns out that QEMU x86 emulated graphic card has a built-in option ROM which can be run perfectly with native mode by U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Update README.x86 for QEMU supportBin Meng2015-06-04-17/+48
| | | | | | | Document how to build and test U-Boot with QEMU. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Update chromebook_link instructions for binary blobSimon Glass2015-04-29-1/+1
| | | | | | | The MRC image is incorrect, or at least this one now does not seem to work. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Correct Minnowboard instructions to use the right descriptorSimon Glass2015-04-29-3/+20
| | | | | | | The descriptor provided with the FSP does not seem to work. Update the instructions to use the descriptor from the original Intel firmware. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add queensbay fsp patch information in README.x86Bin Meng2015-03-24-0/+7
| | | | | | | | | | | The FSP release version 001 for Intel Queensbay has a bug which could cause random endless loop during the FspInit call. This bug was published by Intel although Intel did not describe any details. Describe this information in the x86 doc so that U-Boot Queensbay support is invulnerable. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add Intel Galileo instructions in README.x86Bin Meng2015-02-06-4/+20
| | | | | | | Add some instructions about building U-Boot for Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add support for Intel Minnowboard MaxSimon Glass2015-02-06-5/+42
| | | | | | | | | | | | | | This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add some documentation on how to port U-Boot on x86Simon Glass2015-02-06-0/+64
| | | | | | | | Some information has been gleaned on tools and procedures for porting U-Boot to different x86 platforms. Add a few notes to start things off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an option to enabling building a ROM fileSimon Glass2015-02-05-4/+6
| | | | | | | | | | | Rather than requiring the Makefile to be modified, provide a build option to enable the ROM to be built. We cannot do this by default since it requires binary blobs. Without these the build will fail. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update README.x86 for coreboot supportBin Meng2015-01-13-2/+37
| | | | | | | | Update README.x86 to include new build instructions for U-Boot as the coreboot payload and testing considerations with coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add an 'mtrr' command to list and adjust MTRRsSimon Glass2015-01-13-1/+17
| | | | | | | | | | | | | It is useful to be able to see the MTRR setup in U-Boot. Add a command to list the state of the variable MTRR registers and allow them to be changed. Update the documentation to list some of the available commands. This does not support fixed MTRRs as yet. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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