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* x86: Enable mrc cache for bayleybay and minnowmaxBin Meng2015-10-21-0/+1
| | | | | | | | | | | | Now that we have added MRC cache for Intel FSP and BayTrail codes, enable it for all BayTrail boards (Bayley Bay and Minnow Max). Note it turns out that FSP for Intel Atom E6xx does not produce the HOB for NV storage, so we don't have such functionality on Intel Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Make hob command a sub-command to fspBin Meng2015-10-21-3/+2
| | | | | | | | | Introduce a new fsp command and make the existing hob command a sub-command to fsp for future extension. Also move cmd_hob.c to the dedicated fsp sub-directory in arch/x86/lib. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add SMBIOS table supportBin Meng2015-10-21-2/+0
| | | | | | | | | | | | System Management BIOS (SMBIOS) is a specification for how motherboard and system vendors present management information about their products in a standard format by extending the BIOS interface on Intel architecture systems. As of today the latest spec is 3.0 and can be downloaded from DMTF website. This commit adds a simple and minimum required implementation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* doc: Complement document about booting VxWorksBin Meng2015-10-21-0/+2
| | | | | | | | Current document about how to boot VxWorks is limited. Add several chapters in README.vxworks to document this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* x86: doc: Add DMI to the TODO listBin Meng2015-09-16-0/+2
| | | | | | | | Desktop Management Interface (DMI) is not supported by U-Boot now. Add it to the TODO list. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: doc: Document some porting hints about Intel QuarkBin Meng2015-09-16-0/+24
| | | | | | | | Document porting considerations for Intel Quark based board, including MRC parameters and PCIe initialization. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: doc: Change to use CONFIG_VGA_BIOS_ADDRBin Meng2015-09-09-1/+1
| | | | | | | | | CONFIG_X86_OPTION_ROM_ADDR has been renamed to CONFIG_VGA_BIOS_ADDR. Update the doc to refer to the new name. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Correct microcode documentationSimon Glass2015-08-26-2/+2
| | | | | | | | This is incorrect since we require the -m parameter to the microcode tool. Update the two examples to show this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: doc: Update coreboot payload entry point addressBin Meng2015-08-26-3/+3
| | | | | | | | With recent EFI support, the entry point address of coreboot payload was changed. Now we update the address to use _x86boot_start, which is the same one for EFI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a simple interrupt script to the READMESimon Glass2015-08-14-0/+15
| | | | | | | | | | It is a bit tedious to figure out the interrupt configuration for a new x86 platform. Add a script which can do this, based on the output of 'pci long'. This may be helpful in some cases. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add clarifications to the x86 READMEStoppa, Igor2015-08-14-11/+21
| | | | | | | | | | * Explicitly list the targets supported in each section of the instructions from the x86 README. * Drop references to 'raw mode', in favor of 'bare mode'. Signed-off-by: Igor Stoppa <igor.stoppa@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Document how to write PIRQ information in the device treeBin Meng2015-08-05-0/+41
| | | | | | | | Document the development flow on figuring out PIRQ information during the U-Boot porting. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Update README to explain booting Ubuntu on MinnowmaxSimon Glass2015-08-05-0/+278
| | | | | | | | | | | | | | | | The steps required to boot a Linux distribution from U-Boot on x86 are not very complicated, but it is a good idea to have these written down in an accessible place. Document how to examine the boot media from U-Boot, how to load a kernel, load a ramdisk, set the kernel boot arguments and start the kernel. With these instructions Ubuntu boots mostly normally on Minnowmax. Note that the TSC timer does not operate correctly and gives warnings in the boot log. I expect that ACPI support will solve this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: Add MP initializationBin Meng2015-08-05-0/+5
| | | | | | | | | Add a cpu1 node to the device tree and enable the MP initialization on QEMU targets (i440fx and q35). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Add binary blob checksums for Minnowboard MAXSimon Glass2015-07-14-0/+8
| | | | | | | | | | To try to reduce the pain of confusion of binary blobs, add MD5 checksums for the current versions. This may worsen the situation as new versions appear, but it should still be possible to obtain these versions, and thus get a working setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add ROM image description for minnowmaxSimon Glass2015-07-14-0/+17
| | | | | | | | The layout of the ROM is a bit hard to discover by reading the code. Add a table to make it easier. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: crownbay: Enable graphics supportBin Meng2015-07-14-7/+13
| | | | | | | | | | | Enable graphics support on Intel Crown Bay board With the help of vgabios for Intel TunnelCreek IGD. Tested with an external LVDS panel connected to X4 connector and SDVO adapter connected to X9 connector on the board. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move VGA option rom macros to KconfigBin Meng2015-07-14-1/+1
| | | | | | | | | | Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Update README.x86 for SMP supportBin Meng2015-07-14-0/+13
| | | | | | | | Document U-Boot multi-processor support as well as configuration tables like SFI and MP tables for SMP OS kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Create separate i440fx and q35 device treesBin Meng2015-06-04-1/+9
| | | | | | | | | | Although the two qemu-x86 targets (i440fx and q35) share a lot in common, they still have something that cannot easily handled in one single device tree). Split to create two dedicated device tree files and make the i440fx be the default build target. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Add graphics supportBin Meng2015-06-04-1/+6
| | | | | | | | It turns out that QEMU x86 emulated graphic card has a built-in option ROM which can be run perfectly with native mode by U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Update README.x86 for QEMU supportBin Meng2015-06-04-17/+48
| | | | | | | Document how to build and test U-Boot with QEMU. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Update chromebook_link instructions for binary blobSimon Glass2015-04-29-1/+1
| | | | | | | The MRC image is incorrect, or at least this one now does not seem to work. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Correct Minnowboard instructions to use the right descriptorSimon Glass2015-04-29-3/+20
| | | | | | | The descriptor provided with the FSP does not seem to work. Update the instructions to use the descriptor from the original Intel firmware. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add queensbay fsp patch information in README.x86Bin Meng2015-03-24-0/+7
| | | | | | | | | | | The FSP release version 001 for Intel Queensbay has a bug which could cause random endless loop during the FspInit call. This bug was published by Intel although Intel did not describe any details. Describe this information in the x86 doc so that U-Boot Queensbay support is invulnerable. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add Intel Galileo instructions in README.x86Bin Meng2015-02-06-4/+20
| | | | | | | Add some instructions about building U-Boot for Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add support for Intel Minnowboard MaxSimon Glass2015-02-06-5/+42
| | | | | | | | | | | | | | This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add some documentation on how to port U-Boot on x86Simon Glass2015-02-06-0/+64
| | | | | | | | Some information has been gleaned on tools and procedures for porting U-Boot to different x86 platforms. Add a few notes to start things off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an option to enabling building a ROM fileSimon Glass2015-02-05-4/+6
| | | | | | | | | | | Rather than requiring the Makefile to be modified, provide a build option to enable the ROM to be built. We cannot do this by default since it requires binary blobs. Without these the build will fail. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update README.x86 for coreboot supportBin Meng2015-01-13-2/+37
| | | | | | | | Update README.x86 to include new build instructions for U-Boot as the coreboot payload and testing considerations with coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add an 'mtrr' command to list and adjust MTRRsSimon Glass2015-01-13-1/+17
| | | | | | | | | | | | | It is useful to be able to see the MTRR setup in U-Boot. Add a command to list the state of the variable MTRR registers and allow them to be changed. Update the documentation to list some of the available commands. This does not support fixed MTRRs as yet. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a README.x86 for U-Boot on x86 supportBin Meng2014-12-18-0/+126
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (Use 'Link' as the name for the Chromebook Pixel consistently) Change-Id: I158c88653978ff212334f6d4ffeaf49fa81baefe
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