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| | * | | ColdFire: MCF532x - Update do_reset() using core resetTsiChungLiew2007-11-07-6/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
| | * | | ColdFire: Update cpu flag for 4.2-xx compilerTsiChungLiew2007-11-07-0/+41
| | | | | | | | | | | | | | | | | | | | Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
| * | | | powerpc: Backout relocation changes.Grant Likely2007-11-17-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ugh. I *hate* to back this change out, but these compiler flags don't work for relocation on all versions of GCC. I've not been able to reproduce the environment in my setup (and hence, not been able to find a combination that *does* work), so I've got no choice but to go back to the old gcc flags and linker script. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * | | | 86xx: Fix broken variable reference when #def DEBUGing.Jon Loeliger2007-11-17-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes you can't reference the DDR2 controller variables. Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * | | | make 8610 board use pixis resetJason Jin2007-11-17-2/+2
| |/ / / | | | | | | | | | | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| * | | Cleanup coding style; update CHANGELOGWolfgang Denk2007-11-03-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | Fix a typo in cpu/mpc824x/interrupts.cGuennadi Liakhovetski2007-11-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since December 2003 the timer_interrupt_cpu() function in cpu/mpc824x/interrupts.c contains what seems to be a superfluous parameter. Remove it. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
| * | | add ft_cpu_setup(..) on mpc8260Sergej Stepanov2007-11-03-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ft_cpu_setup(..)-function to adapt it for use with libfdt based on code from mpc5xxx Sigend-off-by: Sergej Stepanov <Sergej.Stepanov@ids.de> --
| * | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2007-11-02-3/+7
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| | * \ \ Merge branch 'master' of git://www.denx.de/git/u-boot-coldfireWolfgang Denk2007-11-01-3/+7
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| | | * | | ColdFire 5329: Assign correct SDRAM size and fix cacheTsiChungLiew2007-10-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
| | | * | | ColdFire 5282: Fix external flash boot and return dramsizeTsiChungLiew2007-10-25-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
| * | | | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2007-11-01-20/+32
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| | * | | | Merge branch 'master' of git://www.denx.de/git/u-boot-mipsWolfgang Denk2007-11-01-7/+14
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| | | * | | | [MIPS] Add PIC-related switches to PLATFORM_{CPP,LD}FLAGS and cleanupShinya Kuribayashi2007-10-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
| | | * | | | [MIPS] Fix $gp usageShinya Kuribayashi2007-10-21-6/+13
| | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we load $gp with _GLOBAL_OFFSET_TABLE_, but this is incorrect use. As a general principle, we should use _gp for $gp. Thanks to linker script's help we fortunately have _gp which equals to _GLOBAL_OFFSET_TABLE_. But once _gp gets out of alignment, we will not be able to access to GOT entires, global variables and procedure entry points. The right thing to do is to use _gp. This patch also introduce a new symbol `.gpword _GLOBAL_OFFSET_TABLE_' which holds the offset from _gp. When updating GOT entries, we use this offset and _gp to calculate the final _GLOBAL_OFFSET_TABLE_. This patch is originally submitted by Vlad Lungu <vlad@comsys.ro>, then I made some change to leave over num_got_entries. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Cc: Vlad Lungu <vlad@comsys.ro>
| | * | | | Setting MSR[DE] in do_reseturwithsughosh@gmail.com2007-10-19-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hello, This patch ensures the soft reset of the board for the 85xx boards by setting the MSR[DE] in the do_reset function. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
| | * | | | MSR overwrite fixurwithsughosh@gmail.com2007-10-19-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hello, This patch fixes the MSR overwrite in the start.S when moving out of the last 4K page. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
| | * | | | Remove magic numbers from cache related operations for mpc85xxKumar Gala2007-10-19-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mpc85xx start code uses some magic numbers that we actually have #defines for in <config.h> so use those instead. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | | | Merge branch 'denx'Andy Fleming2007-10-19-340/+568
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| | * | | | 85xx io out functions need sync after write.Ed Swarthout2007-09-26-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the mc146818 rtc_read/write functions for 85xx. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
* | | | | | ppc4xx: Correct 405EX PCIe UTL register mappingStefan Roese2007-11-18-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Map 4k mem space for UTL registers for each port. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Enable 405EX PCIe UTL register configurationStefan Roese2007-11-16-4/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Till now the UTL registers on 405EX were not initialized but left with their default values. This patch new initializes some of the UTL registers on 405EX. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platformsStefan Roese2007-11-15-78/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - Cleanup of the 4xx GPIO functions - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Fix 405EX PCIe UTLSET register setupStefan Roese2007-11-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Make USB working with CONFIG_4xx_DCACHE definedMatthias Fuchs2007-11-09-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch disables the 44x d-cache on 'usb start' and reenables it on 'usb stop'. This should be seen as a temporary fix until the generic usb-ohci driver can life with d-cache enabled. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Remove redundant code from 4xx network driverMatthias Fuchs2007-11-09-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes some redundant code and decrements the end address of cache flush and invalidate by 1. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Make output a little shorter on I2C bootrom detectionStefan Roese2007-11-09-34/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most 4xx PPC capable of using an I2C bootrom for bootstrap setting already print a line with the information which I2C bootrom is used for bootstrap configuration. So we don't need this extra line with "I2C boot EEPROM en-/dis-abled". This patch also has a little code cleanup integrated. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAMStefan Roese2007-10-31-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Change 4xx ethernet driver to handle cached memory tooStefan Roese2007-10-31-75/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the 4xx EMAC driver to work too, when dcache is enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Add change_tlb function to modify I attribute of TLB(s)Stefan Roese2007-10-31-1/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is used to either turn cache on or off in a specific memory area. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Rework 4xx cache supportStefan Roese2007-10-31-135/+290
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New cache handling functions added and all existing functions moved from start.S into seperate cache.S. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Change autonegotiation timeout from 4 to 5 secondsStefan Roese2007-10-31-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I lately noticed, that newer 4xx board with GBit support sometimes don't finish link autonegotiation in 4 seconds. Changing this timeout to 5 seconds seems fine here. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Change 4xx_enet & miiphy to use out_be32() and friendsStefan Roese2007-10-31-73/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes all in32/out32 calls to use the recommended in_be32/ out_be32 macros instead. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Correct UART input clock calculation and passing to fdtStefan Roese2007-10-31-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We now use a value in the gd (global data) structure for the UART input frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely in get_sys_info(). Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Add initial AMCC Haleakala PPC405EXr eval board supportStefan Roese2007-10-31-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Haleakala is nearly identical with the Kilauea eval board. The only difference is that the 405EXr only supports one EMAC and one PCIe interface. This patch adds support for the Haleakala board by using the identical image for Kilauea and Haleakala. The distinction is done by comparing the PVR. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Rework of 4xx serial driver (4)Stefan Roese2007-10-31-167/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change 4xx_uart.c: - Use in_8/out_8 macros instead of in8/out8 - No need for UART_BASE marco anymore, now really handled via function parameter - serial_init_common() introduced - Further coding style cleanup Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Rework of 4xx serial driver (1)Stefan Roese2007-10-31-208/+243
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch starts the rework of the PPC4xx serial driver. First we split the file into two seperate files, one 4xx_uart.c with the 405/440 UART handling code and the other one iop480_uart.c with the UART code for the PLX-Tech IOP480 PPC (PPC403 based). Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Correct UART input clock calculation and passing to fdtStefan Roese2007-10-31-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Add freqUART to CPU speed detectionStefan Roese2007-10-31-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This value is needed later for the device tree configuration of the uart clock. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xxStefan Roese2007-10-31-34/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Add PCIe endpoint support on Kilauea (405EX)Stefan Roese2007-10-31-10/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds endpoint support for the AMCC Kilauea eval board. It can be tested by connecting a reworked PCIe cable (only 1x lane singles connected) to another root-complex. In this test setup, a 64MB inbound window is configured at BAR0 which maps to 0 on the PLB side. So accessing this BAR0 from the root-complex will access the first 64MB of the SDRAM on the PPC side. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint modeStefan Roese2007-10-31-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for dynamic configuration of PCIe ports for the AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe boards Yucca & Katmai and the 405EX board Kilauea. This dynamic configuration is done via the "pcie_mode" environement variable. This variable can be set to "EP" or "RP" for endpoint or rootpoint mode. Multiple values can be joined via the ":" delimiter. Here an example: pcie_mode=RP:EP:EP This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2 as endpoint. Per default Yucca will be configured as: pcie_mode=RP:EP:EP Per default Katmai will be configured as: pcie_mode=RP:RP:REP Per default Kilauea will be configured as: pcie_mode=RP:RP Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Add additional debug info to 4xx fdt supportStefan Roese2007-10-31-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Fix small merge problem in 4xx_enet.cStefan Roese2007-10-31-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Add PPC405EX supportStefan Roese2007-10-31-100/+532
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Cleanup of 4xx PCI and PCIe support (renaming)Stefan Roese2007-10-31-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Add initial fdt support to 4xx (first needed on 405EX)Stefan Roese2007-10-31-0/+171
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: 4xx_pcie: Change PCIe status output to match common styleStefan Roese2007-10-31-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: 4xx_pcie: Disable debug output as defaultStefan Roese2007-10-31-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-11-07 15:51:02 +0000