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* ppc4xx: Add functionality to GPIO supportLawrence R. Johnson2008-01-04-23/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes two additions to GPIO support: First, it adds function gpio_read_in_bit() to read the a bit from the GPIO Input Register (GPIOx_IR) in the same way that function gpio_read_out_bit() reads a bit from the GPIO Output Register (GPIOx_OR). Second, it modifies function gpio_set_chip_configuration() to provide an additional option for configuring the GPIO from the "CFG_4xx_GPIO_TABLE". According to the 440EPx User's Manual, when an alternate output is used, the three-state control is configured in one of two ways, depending on the particular output. The first option is to select the corresponding alternate three-state control in the GPIOx_TRSH/L registers. The second option is to select the GPIO Three-State Control Register (GPIOx_TCR) in the GPIOx_TRSH/L registers, and set the corresponding bit in the GPIOx_TCR register to enable the output. For example, the Manual specifies configuring the GPIO00 Alternate 1 Signal (PreAddr07) to use the alternate three-state control (first option), and specifies configuring the GPIO32 Alternate 1 Signal (USB2OM0) with the output enabled in the GPIOx_TCR register (second option). Currently, gpio_set_chip_configuration() configures all alternate signal outputs to use the first option. This patch allow the second option to be selected by setting the "out_val" element in the table entry to "GPIO_OUT_1". The first option is used when the "out_val" element is set to "GPIO_OUT_0". Because "out_val" is not currently used when an alternate signal is selected, and because all current GPIO tables set "out_val" to "GPIO_OUT_0" for all alternate signals, this patch should not change any existing configurations. Signed-off-by: Larry Johnson <lrj@acm.org>
* Merge commit 'wd/master'Jon Loeliger2008-01-03-1844/+4559
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| * ppc4xx: Enable 405EP PCI arbiter per default on all boardsStefan Roese2007-12-28-0/+5
| | | | | | | | | | | | | | | | | | | | In an attmemt to clean up the 4xx start.S file, I removed the enabling of the internal 405EP PCI arbiter. This is needed for multiple other 405EP platforms, like most of the esd 405EP. Now the internal PCI arbiter is enabled again per default as it has been before. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * ppc4xx: Fix bug in cpu_init.c (405EP instead of 450EP)Stefan Roese2007-12-28-1/+1
| | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * Merge branch 'master' of /home/stefan/git/u-boot/u-boot into for-1.3.2-ver2Stefan Roese2007-12-27-259/+739
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| | * Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2007-12-27-4/+1
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| | | * TQM885D: Exchanged SDRAM timing by a more relaxed timing.Jens Gehrlein2007-12-27-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CAS-Latency=2, Write Recovery Time tWR=2 The max. supported bus frequency is 66 MHz. Therefore, changed threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz. Signed-off-by: Martin Krause <martin.krause@tqs.de>
| | * | Fix coding style issues; update CHANGELOG.Wolfgang Denk2007-12-27-44/+40
| | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2007-12-27-0/+529
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| | | * Merge branch 'master' of git://www.denx.de/git/u-boot-shWolfgang Denk2007-12-27-0/+529
| | | |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: MAINTAINERS Signed-off-by: Wolfgang Denk <wd@denx.de>
| | | | * Merge git://www.denx.de/git/u-bootNobuhiro Iwamatsu2007-12-07-61/+17
| | | | |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/Makefile
| | | | * \ Merge git://www.denx.de/git/u-bootNobuhiro Iwamatsu2007-11-29-341/+392
| | | | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/Makefile
| | | | * | | sh: Update core code of SuperH.Nobuhiro Iwamatsu2007-09-23-22/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | | * | | Merge git://www.denx.de/git/u-bootNobuhiro Iwamatsu2007-09-23-5470/+14939
| | | | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: CREDITS
| | | | * | | | sh: First support code of SuperH.Nobuhiro Iwamatsu2007-05-13-0/+399
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * | | | | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2007-12-27-7/+15
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| | | * | | | | Merge branch 'master' of git://www.denx.de/git/u-boot-avr32Wolfgang Denk2007-12-27-7/+15
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| | | | * | | | | AVR32: Fix wrong pin setup for USART3Haavard Skinnemoen2007-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported by Gerhard Berghofer: in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18 instead of PB18 and PB19. which is obviously correct. There's currently no code that uses USART3, but custom boards may run into problems. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| | | | * | | | | AVR32: Make some AT32AP700x peripherals optionalHaavard Skinnemoen2007-12-17-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a chip-features file providing definitions of the form AT32AP700x_CHIP_HAS_<peripheral> to indicate the availability of the given peripheral on the currently selected chip. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| | | | * | | | | AVR32: Rename at32ap7000 -> at32ap700xHaavard Skinnemoen2007-12-17-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SoC-specific code for all the AT32AP700x CPUs is practically identical; the only difference is that some chips have less features than others. By doing this rename, we can add support for the AP7000 derivatives simply by making some features conditional. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| | | | * | | | | atmel_mci: Show SR when block read failsHaavard Skinnemoen2007-12-17-6/+7
| | | | | |_|_|/ | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Show controller status as well as card status when an error occurs during block read. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| | * | | | | | Handle Asynchronous DDR clock on 85xxKumar Gala2007-12-11-4/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8572 introduces the concept of an asynchronous DDR clock with regards to the platform clock. Introduce get_ddr_freq() to report the DDR freq regardless of sync/async mode. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | | | | | Stop using immap_t on 85xxKumar Gala2007-12-11-32/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | | | | | Remove CONFIG_OF_FLAT_TREE related code from mpc85xx since we now use libfdtKumar Gala2007-12-11-123/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | | | | | Stop using immap_t for cpm offset on 85xxKumar Gala2007-12-11-66/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers instead of getting it via &immap->im_cpm. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | | | | | Stop using immap_t for guts offset on 85xxKumar Gala2007-12-11-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers instead of getting it via &immap->im_gur. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | | | | | Add libfdt based ft_cpu_setup for mpc85xxKumar Gala2007-12-11-1/+67
| | |/ / / / / | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | | | | Convert boards that set memory node to use fdt_fixup_memory()Kumar Gala2007-12-07-16/+2
| | |/ / / / | | | | | | | | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | | | Add denali_data_eye.o and denali_spd_ddr2.o to PPC4xx MakefileLarry Johnson2007-12-27-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Larry Johnson <lrj@acm.org>
| * | | | | Add 440EPx DDR2 SPD DIMM supportLarry Johnson2007-12-27-0/+1254
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM controller. It should also work on the 440GRx. It is based on the DDR2 SPD code for the 440EP/440EPx, but makes no provision for DDR1 support. This code has been tested on prototype Korat boards with three Kingston DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC (two ranks). The Korat board has a single DIMM socket, but support has been provided (though not tested) for boards with two DIMM sockets. Signed-off-by: Larry Johnson <lrj@acm.org>
| * | | | | Copy 440EPx/GRx SDRAM data-eye search to common directoryLarry Johnson2007-12-27-0/+396
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch creates a non-board-specific file for performing the SDRAM data-eye search. It also adds ECC error checking to the test of valid data on readback when ECC is enabled. Signed-off-by: Larry Johnson <lrj@acm.org>
| * | | | | Add Ethernet 1000BASE-X support for PPC4xxLarry Johnson2007-12-27-52/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new switch: "CONFIG_PHY_DYNAMIC_ANEG". When this symbol is defined, the PHY will advertise it's capabilities for autonegotiation based on the capabilities shown in the PHY's status registers, including 1000BASE-X. When "CONFIG_PHY_DYNAMIC_ANEG" is not defined, the PHY will advertise hard-coded capabilities, as before. Signed-off-by: Larry Johnson <lrj@acm.org>
| * | | | | ppc4xx: fdt: Cleanup setup of cpu node setupStefan Roese2007-12-27-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now the cpu node setup ("timebase-frequency" and "clock-frequency") is without using the absolute path to the cpu node. This makes it possible to use this U-Boot version with both versions of cpu-node naming "cpu@0" and the former "PowerPC,440EPx@0". Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | Fix ppc4xx clear_bss() codeAnatolij Gustschin2007-12-27-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ppc4xx clear_bss() fails if BSS segment size is not divisible by 4 without remainder. This patch provides fix for this problem. Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | | | | PPC4xx: Minimal changes to add vxWorks supportNiklaus Giger2007-12-27-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
| * | | | | ppc4xx: fix flush + invalidate_dcache_range argumentsMatthias Fuchs2007-12-27-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flush + invalidate_dcache_range() expect the start and stop+1 address. So the stop address is the first address behind (!) the range. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * | | | | ppc4xx: fdt: use fdt_fixup_ethernet()Stefan Roese2007-12-27-71/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By using aliases in the dts file, the ethernet node fixup is much easier with the recently added functions. Please note that the dts file needs the aliases for this to work. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | ppc4xx: Bring 4xx fdt support up-to-dateStefan Roese2007-12-27-80/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch update the 4xx fdt support. It enabled fdt booting on the AMCC Kilauea and Sequoia for now. More can follow later quite easily. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | ppc4xx: Correct GPIO offset in gpio_config()Stefan Roese2007-12-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Thanks to Gary Jennejohn for pointing this out. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | Merge commit 'u-boot/master' into for-1.3.1Stefan Roese2007-12-11-196/+246
| |\ \ \ \ \ | | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/rtc/Makefile
| * | | | | ppc4xx: Correct 405EX PCIe UTL register mappingStefan Roese2007-11-18-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Map 4k mem space for UTL registers for each port. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | ppc4xx: Enable 405EX PCIe UTL register configurationStefan Roese2007-11-16-4/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Till now the UTL registers on 405EX were not initialized but left with their default values. This patch new initializes some of the UTL registers on 405EX. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platformsStefan Roese2007-11-15-78/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - Cleanup of the 4xx GPIO functions - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | ppc4xx: Fix 405EX PCIe UTLSET register setupStefan Roese2007-11-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | ppc4xx: Make USB working with CONFIG_4xx_DCACHE definedMatthias Fuchs2007-11-09-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch disables the 44x d-cache on 'usb start' and reenables it on 'usb stop'. This should be seen as a temporary fix until the generic usb-ohci driver can life with d-cache enabled. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | ppc4xx: Remove redundant code from 4xx network driverMatthias Fuchs2007-11-09-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes some redundant code and decrements the end address of cache flush and invalidate by 1. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | ppc4xx: Make output a little shorter on I2C bootrom detectionStefan Roese2007-11-09-34/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most 4xx PPC capable of using an I2C bootrom for bootstrap setting already print a line with the information which I2C bootrom is used for bootstrap configuration. So we don't need this extra line with "I2C boot EEPROM en-/dis-abled". This patch also has a little code cleanup integrated. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAMStefan Roese2007-10-31-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | ppc4xx: Change 4xx ethernet driver to handle cached memory tooStefan Roese2007-10-31-75/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the 4xx EMAC driver to work too, when dcache is enabled. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | ppc4xx: Add change_tlb function to modify I attribute of TLB(s)Stefan Roese2007-10-31-1/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is used to either turn cache on or off in a specific memory area. Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-11-09 21:53:30 +0000