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* [MIPS] Request for the 'mips_cache_lock()' removalShinya Kuribayashi2008-03-25-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial intension of having mips_cache_lock() was to use the cache as memory for temporary stack use so that a C environment can be set up as early as possible. But now mips_cache_lock() follow lowlevel_init(). We've already have the real memory initilaized at this point, therefore we could/should use it. No reason to lock at all. Other problems: Cache locking is not consistent across MIPS implementaions. Some imple- mentations don't support locking at all. The style of locking varies - some support per line locking, others per way, etc. Some parts use bits in status registers instead of cache ops. Current mips_cache_lock() is not necessarily general-purpose. And this is worthy of special mention; once U-Boot/MIPS locks the lines, they are never get unlocked, so the code relies on whatever gets loaded after U-Boot to re-initialize the cache and clear the locks. We're sup- posed to have CFG_INIT_RAM_LOCK and unlock_ram_in_cache() implemented, but leave the situation as it is for a long time. For these reasons, I proposed the removal of mips_cache_lock() from the global start-up code. This patch adds CFG_INIT_RAM_LOCK_MIPS to make existing users aware that *things have changed*. If he wants the same behavior as before, he needs to have CFG_INIT_RAM_LOCK_MIPS in his config file. If we don't have any regression report through several releases, then we'll remove codes entirely. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Acked-by: Andrew Dyer <amdyer@gmail.com>
* LWMON5: POST RTC fixYuri Tikhonov2008-03-20-1/+3
| | | | | | | | | | | | | | | | | Modify the RTC API to provide one a status for the time reported by the rtc_get() function: 0 - a reliable time is guaranteed, < 0 - a reliable time isn't guaranteed (power fault, clock issues, and so on). The RTC chip drivers are responsible for providing this info if the corresponding chip supports such functionality. If not - always report that the time is reliable. The POST RTC test was modified to detect the RTC faults utilizing this new rtc_get() feature. Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* ppc4xx: Add Canyonlands NAND booting supportStefan Roese2008-03-15-1/+7
| | | | | | | | | | | | | | | 460EX doesn't support a fixed bootstrap option to boot from 512 byte page NAND devices. The only bootstrap option for NAND booting is option F for 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap EEPROM needs to be programmed accordingly. This patch adds basic NAND booting support for the AMCC Canyonlands aval board and also adds support to the "bootstrap" command, to enable NAND booting I2C setting. Tested with 512 byte page NAND device (32MByte) on Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add basic support for AMCC 460EX/460GT (2/5)Stefan Roese2008-03-15-7/+178
| | | | | | This patch adds basic support for the AMCC 460EX/460GT PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add basic support for AMCC 460EX/460GT (1/5)Stefan Roese2008-03-15-93/+553
| | | | | | This patch adds basic support for the AMCC 460EX/460GT PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: interrupt.c reworkedStefan Roese2008-03-15-448/+141
| | | | | | | | This patch is a rework of the 4xx interrupt handling done while adding the 460EX/GT support. Interrupts are needed on 4xx for the EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: program_tlb now uses 64bit physical addessStefan Roese2008-03-15-13/+14
| | | | | | | | This patch changes the physical addess parameter from 32bit to 64bit. This is needed for 36bit 4xx platforms to access areas located beyond the 4GB border, like SoC peripherals (EBC etc.). Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: miiphy.c reworkedStefan Roese2008-03-15-116/+80
| | | | | | | While adding the 460EX/GT support I reworked the 4xx miiphy code. It badly neede some cleanup. Signed-off-by: Stefan Roese <sr@denx.de>
* PPC4xx (Sequoia): Fix Ethernet "remote fault" problemsMike Nuss2008-03-04-3/+2
| | | | | | | | | | | | | | Every now and then a Sequoia board (or equivalent hardware) had problems connecting to a Gigabit capable network interface. There were differences in the PHY setup between Linux and U-Boot. This patch fixes the problem. Apparently "remote fault" is being set, which signals to some devices (on the other end of the cable) that a fault has occurred, while other devices ignore it. I believe the RF bit was causing the issue, but I removed T4 also, to match up with Linux. Signed-off-by: Mike Nuss <mike@terascala.com>
* ppc4xx: EMAC: Fix 405EZ fifo size setup in EMAC_MR1Stefan Roese2008-03-02-2/+3
| | | | | | | | | The 405EZ only supports 512 bytes of rx-/tx-fifo EMAC sizes. But currently 4k/2k is configured. This patch fixes this issue. Thanks to Thomas Kindler <tkindler@lenord.de> for pointing this out. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxWolfgang Denk2008-03-02-6/+14
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| * 85xx: Don't icbi when unlocking the cacheKumar Gala2008-02-27-5/+2
| | | | | | | | | | | | | | | | | | There is no reason to icbi when invalidating the temporary stack in the d-cache. Its impossible on e500 to have the i-cache contain any addresses in the temp stack and it can be problematic in generating transactions on the bus to non-valid addresses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * Fix source for ECM error IVPRAndy Fleming2008-02-27-1/+1
| | | | | | | | | | | | | | | | The source vector for the ECM was being set to 2, but that's what the source vector for DDR was being set to. Change it to 1. Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Invalidate INIT_RAM TLB mappingsAndy Fleming2008-02-27-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 0db37dc... (and some others) changed the INIT_RAM TLB mappings to be unguarded. This collided with an existing "bug" where the mappings for the INIT_RAM were being kept around. This meant that speculative loads to those addresses were succeeding in the TLB, and going out to the bus, where they were causing an exception (there's nothing at that address). The Flash code was coincidentally causing such a speculative load. Rather than go back to mapping the INIT RAM as guarded, we fix it so that the entries for the INIT_RAM are invalidated. Thus the speculative loads will fail in the TLB, and have no effect. Signed-off-by: Andy Fleming <afleming@freescale.com>
* | MPC5121e ADS PCI support take 3John Rigby2008-03-02-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds PCI support for MPC5121 Tested with drivers/net/rtl8139.c Support is conditional since PCI on old silicon does not work. ads5121_PCI_config turns on PCI In this version, condition compilation of PCI code has been moved from ifdef in board/ads5121/pci.c to board/ads5121/Makefile as suggested by Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: John Rigby <jrigby@freescale.com>
* | ppc4xx: Fix problem in 4xx_enet.c driverAnatolij Gustschin2008-03-02-1/+9
|/ | | | | | | | | | U-Boot crashes in the net loop if CONFIG_4xx_DCACHE is enabled. To reproduce the problem ensure that 'ethrotate' environment variable isn't set to "no" and then run "tftp 200000 not_existent_file". This patch tries to fix the issue. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* Coding style cleanup. Prepare v1.3.2-rc2 release candidateWolfgang Denk2008-02-24-8/+10
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* cpu/mcf52x2/config.mk: Make needlessly deffered expansions immediate.Shinya Kuribayashi2008-02-23-5/+5
| | | | | | This will reduce the build time. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* cpu/ppc4xx/config.mk: Make a needlessly deffered expansion immediate.Shinya Kuribayashi2008-02-23-1/+1
| | | | | | This will reduce the build time. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* cpu/mips/cofigl.mk: Make a needlessly deffered expansion immediate.Shinya Kuribayashi2008-02-23-1/+1
| | | | | | | | | | | This reduces the build time by ~10%. Here's the gth2_config example. BEFORE AFTER real 0m31.441s 0m27.833s user 0m24.766s 0m23.045s sys 0m10.425s 0m7.468s Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xxWolfgang Denk2008-02-22-70/+54
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| * 86xx: Convert sbc8641d to use libfdt.Jon Loeliger2008-02-18-66/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the proper fix for a missing closing brace in the function ft_cpu_setup() noticed by joe.hamman <at> embeddedspecialties.com. The ft_cpu_setup() function in mpc8641hpcn.c should have been removed earlier as it was under the obsolete CONFIG_OF_FLAT_TREE, but was missed. Only, the sbc8641d was nominally still using it. It all got ripped out, and the funcality that was in ft_board_setup() was refactored to remove the CPU portions into the new file cpu/mpc86xx/fdt.c instead. Make sbc8641d use this now. Based loosely on an original patch from joe.hamman@embeddedspecialties.com Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * mpc86xx: Fix unused variable 'config' and 'immap'Jean-Christophe PLAGNIOL-VILLARD2008-02-18-4/+6
| | | | | | | | | | | | and remove useless CONFIG_DDR_INTERLEAVE Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * mpc86xx: Fix implicit declaration of functions 'init_laws' and 'disable_law'Jean-Christophe PLAGNIOL-VILLARD2008-02-18-0/+1
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ColdFire: Fix 5282 and 5271 interrupt mask bitTsiChungLiew2008-02-20-1/+1
|/ | | | Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* s3c24x0: Fix unused variable 'i' in function 'serial_init_dev'Jean-Christophe PLAGNIOL-VILLARD2008-02-17-1/+0
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* pxa: fix assignment from incompatible pointer typeJean-Christophe PLAGNIOL-VILLARD2008-02-17-1/+1
| | | | | | fix mmc_bread function prototype Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Merge branch '080208_dupint' of git://linux-arm.org/u-boot-armdevPeter Pearse2008-02-15-1613/+10
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| * ARM: cleanup duplicated exception handlingcodeAndreas Engel2008-02-14-1613/+10
| | | | | | | | | | | | Move duplicated exception handling code into lib_arm. Signed-off-by: Andreas Engel <andreas.engel@ericsson.com>
* | Merge branch '080116_at91cap9' of git://linux-arm.org/u-boot-armdevPeter Pearse2008-02-15-3/+455
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| * | AT91CAP9 support : cpu/ filesStelian Pop2008-02-14-1/+452
| | | | | | | | | | | | Signed-off-by: Stelian Pop <stelian <at> popies.net>
| * | Fix arm926ejs compile when SKIP_LOWLEVEL_INIT is onStelian Pop2008-02-14-2/+3
| |/ | | | | | | | | | | | | | | | | Fix arm926ejs compile when SKIP_LOWLEVEL_INIT is on. cpu/arm926ejs/start.o: In function `cpu_init_crit': .../cpu/arm926ejs/start.S:227: undefined reference to `lowlevel_init' Signed-off-by: Stelian Pop <stelian@popies.net>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-armWolfgang Denk2008-02-15-4/+9
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| * | Fix timer overflow in DaVinciPeter Pearse2008-02-14-4/+9
| |/ | | | | | | Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xxWolfgang Denk2008-02-15-79/+108
|\ \ | | | | | | | | | | | | | | | | | | | | | Conflicts: common/cmd_reginfo.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * \ Merge commit 'wd/master'Jon Loeliger2008-02-14-2/+0
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| * | Merge commit 'wd/master'Jon Loeliger2008-02-13-209/+688
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| * | | 86xx: Add reginfo commandBecky Bruce2008-01-24-1/+23
| | | | | | | | | | | | | | | | Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * | | 86xx: Remove old-style law setup codeBecky Bruce2008-01-24-32/+0
| | | | | | | | | | | | | | | | | | | | | | | | This includes mpc8610hpcd, mpc8641hpcn, and sbc8641d. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * | | 86xx: Support new law setup method and convert mpc8641Becky Bruce2008-01-24-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the support code in cpu/mpc86xx for the new law setup code recently created fsl_law.c, and changes the MPC8641HPCN config to use this code. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * | | 86xx: Rearrange the sequence in start.SBecky Bruce2008-01-24-53/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * split the BAT initialization so that only 2 BATs (for the boot page and stack) are programmed very early on. The rest are initialized later. * Move other BAT setup, ccsrbar setup, and law setup later in the code after translation has been enabled. These changes will facilitate the moving of law and BAT initialization to C code, and will aid with 36-bit physical addressing support. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xxWolfgang Denk2008-02-15-5/+9
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| * \ \ \ Merge branch 'for-1.3.2'Stefan Roese2008-02-14-5/+9
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| | * | | ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD codeLarry Johnson2008-02-14-3/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Larry Johnson <lrj@acm.org>
| | * | | ppc4xx: Fix ndfc HW ECC byte orderStefan Roese2008-02-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ndfc HW ECC implementation swaps the first two ECC bytes. But the 4xx NDFC already uses the SMC (Smart Media Card) ECC ordering, so this swapping in the HW ECC driver is bogus. This patch fixes this problem and now really uses the SMC ECC byte order. Thanks to Sean MacLennan for pointing this out. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | ppc4xx: Fix problem with init-ram bigger than 4k on 440 platformsStefan Roese2008-02-04-0/+4
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | Merge branch 'master' of git://www.denx.de/git/u-boot-avr32Wolfgang Denk2008-02-15-1/+5
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| * | | | | AVR32: Make SDRAM refresh rate configurableHaavard Skinnemoen2008-02-05-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing code assumes the SDRAM row refresh period should always be 15.6 us. This is not always true, and indeed on the ATNGW100, the refresh rate should really be 7.81 us. Add a refresh_period member to struct sdram_info and initialize it properly for both ATSTK1000 and ATNGW100. Out-of-tree boards will panic() until the refresh_period member is updated properly. Big thanks to Gerhard Berghofer for pointing out this issue. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* | | | | | Merge branch 'master' of git://www.denx.de/git/u-boot-blackfinWolfgang Denk2008-02-15-400/+283
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: Makefile doc/README.standalone Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | | | | scrub unused symbolsMike Frysinger2008-02-04-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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