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* 85xx: Add support for 'cpu disable' commandKumar Gala2010-01-26-2/+26
| | | | | | Support disabling of a core via user command 'cpu disable'. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 86xx: Add support for 'cpu disable' commandKumar Gala2010-01-26-2/+16
| | | | | | Support disabling of a core via user command 'cpu disable'. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add support to disable cpu's in multicore processorsKumar Gala2010-01-26-1/+35
| | | | | | | | | | | Add a disable sub-command to the cpu command that allows for disabling cores in multicore processors. This can be useful for systems that are using multicore chips but aren't utilizing all the cores as a way to reduce power and possibly improve performance. Also updated an added missing copyright. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2010-01-26-9/+32
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| * qe: fixup the snum for MPC8569 Rev2.0Liu Yu2010-01-25-0/+18
| | | | | | | | | | | | | | | | Since 1.0 and 2.0 use different snum table, we fixup the snum value according to SPRN_SVR. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * Fix the local bus divider mappingDave Liu2010-01-25-1/+6
| | | | | | | | | | | | | | | | The real clock divider is 4 times of the bits LCRR[CLKDIV], according the latest RevF RM. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * Revert "ppc/p4080: Fix reporting of PME & FM clock frequencies"Kumar Gala2010-01-25-6/+6
| | | | | | | | | | | | | | | | | | This reverts commit bc20f9a9527afe8ae406a74f74765d4323f04922. The original code was correct. I clearly need glasses or a brown paper bag. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/p4080: Fix mask width of RCW fields MEM_PLL_RAT, SYS_PLL_RATJames Yang2010-01-25-2/+2
| | | | | | | | | | | | | | | | The masks for MEM_PLL_RAT and SYS_PLL_RAT should have been 5-bits instead of 4. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc: remove -ffixed-r14 gcc option.Joakim Tjernlund2010-01-26-12/+12
| | | | | | | | | | | | This is no loger needed, free up r14 for general usage. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
* | ppc: Use r12 instead of r14 as GOT pointer.Joakim Tjernlund2010-01-26-61/+75
| | | | | | | | | | | | | | | | r14 is not supposed to be clobbered by functions. Switch to r12 and call GET_GOT when needed. This will allow u-boot to loose the -ffixed-r14 gcc option. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
* | ppc: Loose GOT access in IRQJoakim Tjernlund2010-01-26-382/+36
|/ | | | | | | | Using the GOT in IRQ handlers requires r14 to be -ffixed-r14. Avoid this by relocatate transfer_to_handler too. This will allow to free up r14 later on. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
* mpc5xxx: Support CPU internal watchdog.Detlev Zundel2010-01-25-2/+32
| | | | Signed-off-by: Detlev Zundel <dzu@denx.de>
* mpc512x: Add display of reset status registerDetlev Zundel2010-01-24-2/+3
| | | | | | | | Content of the RSR is put into gd early so we can output it together with the CPU info. The clearing of gd in board_init_f is redundant for this architecture as it is done in cpu_init_f so we remove it. Signed-off-by: Detlev Zundel <dzu@denx.de>
* SPEAr : Adding basic SPEAr architecture support.Vipin KUMAR2010-01-23-0/+259
| | | | | | | | | | SPEAr Architecture support added. It contains the support for following SPEAr blocks - Timer - System controller - Misc registers Signed-off-by: Vipin <vipin.kumar@st.com>
* Kirkwood: Makefile cleanup- fixed ordering (cosmetic change)Prafulla Wadaskar2010-01-23-2/+2
| | | | | | | | | | | As per coding guidlines, it is good to maintain proper ordering in the makefiles. This was missed during initial coding, corrected here. This was discovered during orion5x code review Thanks to Albert Aribaud for this. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* s5pc1xx: update cache routinesMinkyu Kang2010-01-23-45/+122
| | | | | | | | | | Because of v7_flush_dcache_all is moved to omap3/cache.S and s5pc110 needs cache routines, update s5pc1xx cache routines. l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S and invalidate_dcache is modified for SoC specific. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* mpc512x: Use in/out accessors for all registersDetlev Zundel2010-01-21-18/+19
| | | | | | | This is not only a cosmetic change as it fixes the real bug of board reset not working with the ELDK 4.2 toolchain. Signed-off-by: Detlev Zundel <dzu@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2010-01-21-2/+2
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| * ppc4xx: Allow setting a single SPD EEPROM address for DDR2 DIMMsFelix Radensky2010-01-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On platforms where SPD EEPROM and another EEPROM have adjacent I2C addresses SPD_EEPROM_ADDRESS should be defined as a single element array, otherwise DDR2 setup code would fail with the following error: ERROR: Unknown DIMM detected in slot 1 However, fixing SPD_EEPROM_ADDRESS would result in another error: ERROR: DIMM's DDR1 and DDR2 type can not be mixed. This happens because initdram() routine does not explicitly initialize dimm_populated array. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GTFelix Radensky2010-01-21-1/+1
| | | | | | | | | | | | | | | | Bootstrap options G and F are reported incorrectly (G instead of F and vice versa). This patch fixes this. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Blackfin: add support for kgdbRobin Getz2010-01-17-5/+157
|/ | | | | Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* kgdb: drop duplicate debugger_exception_handlerMike Frysinger2010-01-18-36/+0
| | | | | | | The debugger_exception_handler definition is the same for everyone, so use the common one now. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* mpc5xxx/cpu_init.c: Convert to IO accessors.Detlev Zundel2010-01-18-48/+78
| | | | Signed-off-by: Detlev Zundel <dzu@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2010-01-17-153/+314
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| * Blackfin: handle anomaly 05000257Robin Getz2010-01-17-1/+10
| | | | | | | | | | | | | | Need to reload the loop counters to keep from corrupting hardware loops. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: keep hwtrace on CPLB missRobin Getz2010-01-17-0/+9
| | | | | | | | | | | | | | | | | | Crashes rarely happen in the CPLB miss handler compared to the rest of U-Boot code, so disable hardware tracing when processing misses. This way a crash due to other functions will be shown properly. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: use new bfin read/write mmr helper funcsMike Frysinger2010-01-17-79/+90
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: move watchdog config check to MakefileMike Frysinger2010-01-17-4/+2
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: support boards with no external memoryMike Frysinger2010-01-17-1/+21
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: re-architect initcodeMike Frysinger2010-01-17-52/+169
| | | | | | | | | | | | | | | | The single initcode function was growing unwieldy, so split it up the distinct steps into their own function. This should making digesting the result much easier on people. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: move section length calculation to linker scriptMike Frysinger2010-01-17-16/+13
| | | | | | | | | | | | | | The length of the sections is fixed at link time, so let the linker do the calculation rather than doing it ourselves at runtime. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | PCIe, USB: Replace 'end point' references with 'endpoint'Peter Tyser2010-01-17-2/+2
|/ | | | | | | | | When referring to PCIe and USB 'endpoint' is the standard naming convention. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Remy Bohmer <linux@bohmer.net>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2010-01-12-0/+21
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| * mpc83xx: add support configure bus parkingHeiko Schocher2010-01-07-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Add support to configure bus parking mode and master in bus arbitration configuration (ACR). Add this for the kmeter1 port: Configure bus arbiter with recommended values from Freescale to improve bus latency/throughput for application with intensive QuiccEngine activity. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * mpc83xx: spd_sdram.c: Disable memory controller before initializingStefan Roese2010-01-07-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory controller could already be enabled, when spd_sdram() is called. This could be the case for example, when the SDRAM is initialized by the JTAG debugger. The "sync" after the register access via the accessor function is still needed, because the macro uses the sync before the real write is done. So until not all accesses are converted to using accessor functions, this sync still needs to be made "manually" here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd.eu> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleaveDave Liu2010-01-05-0/+3
| | | | | | | | | | | | | | | | In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl-ddr: add override for the Rtt_WrDave Liu2010-01-05-3/+7
| | | | | | | | | | | | | | | | | | Different boards may require different settings of Dynamic ODT (Rtt_Wr). We provide a means to allow the board specific code to provide its own value of Rtt_Wr. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl-ddr: add the override for write levelingDave Liu2010-01-05-6/+15
| | | | | | | | | | | | | | | | add the override for write leveling sampling and start time according to specific board. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl-ddr: Fix power-down timing settingsDave Liu2010-01-05-3/+4
| | | | | | | | | | | | | | | | | | | | | | 1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but It should be set to tXP parameter, tXP=max(3CK, 7.5ns) 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter We are setting the mode register MR0[A12]='1' Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/p4080: Fix reporting of PME & FM clock frequenciesKumar Gala2010-01-05-6/+6
| | | | | | | | | | | | | | We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL backwards so we report the wrong frequency. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Map boot page guarded for MP bootKumar Gala2010-01-05-3/+3
| | | | | | | | | | | | | | We already map the page cache-inhibited. There is no reason we shouldn't also be marking it guarded to prevent speculative accesses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | p4080: add readback to bootpage translation windowDave Liu2010-01-05-0/+3
| | | | | | | | | | | | | | | | | | We need to add the readback to bootpage translation LAW to make it effect. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocationKumar Gala2010-01-05-6/+6
| | | | | | | | | | | | | | | | Now that we track which TLB CAM entries are used we can allocate entries on the fly. Change the SPD DDR TLB setup code to assume we use at most 8 TLBs (or the number free, which ever is fewer). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: Add tracking of TLB CAM usageKumar Gala2010-01-05-0/+65
| | | | | | | | | | | | | | | | | | We need to track which TLB CAM entries are used to allow us to "dynamically" allocate entries later in the code. For example the SPD DDR code today hard codes which TLB entries it uses. We can now make that pick entries that are free. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/8xxx: Remove is_fsl_pci_agentKumar Gala2010-01-05-41/+3
| | | | | | | | | | | | | | | | All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent that uses the standard PCI programming model to determine host vs agent/end-point. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | 85xx: Add support to set DPAA (data path) devices clock frequenciesKumar Gala2010-01-05-0/+36
| | | | | | | | | | | | Set clock-frequency for Frame Manager 0/1 and Patter Match Engine on p4080. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/8xxx: Don't use pci_cfg on FSL_CORENET platformsKumar Gala2010-01-05-0/+3
| | | | | | | | | | | | | | The FSL_CORENET platforms use a completely different means to determine which PCIe port is enabled as well as if its a host or agent/end-point. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | 85xx: Add support for e500mc cache stashingKumar Gala2010-01-05-1/+43
|/ | | | | | | | | | | | | | The e500mc core supports the ability to stash into the L1 or L2 cache, however we need to uniquely identify the caches with an id. We use the following equation to set the various stash-ids: 32 + coreID*2 + 0(L1) or 1(L2) The 0 (for L1) or 1 (for L2) matches the CT field used be various cache control instructions. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* USB Consolidate descriptor definitionsTom Rix2009-12-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The header files usb.h and usbdescriptors.h have the same nameed structure definitions for usb_config_descriptor usb_interface_descriptor usb_endpoint_descriptor usb_device_descriptor usb_string_descriptor These are out right duplicates in usb.h usb_device_descriptor usb_string_descriptor This one has extra unused elements usb_endpoint_descriptor unsigned char bRefresh unsigned char bSynchAddress; These in usb.h have extra elements at the end of the usb 2.0 specified descriptor and are used. usb_config_descriptor usb_interface_descriptor The change is to consolidate the definition of the descriptors to usbdescriptors.h. The dublicates in usb.h are removed. The extra element structure will have their name shorted by removing the '_descriptor' suffix. So usb_config_descriptor -> usb_config usb_interface_descriptor -> usb_interface For these, the common descriptor elements are accessed now by an element 'desc'. As an example - if (iface->bInterfaceClass != USB_CLASS_HUB) + if (iface->desc.bInterfaceClass != USB_CLASS_HUB) This has been compile tested on MAKEALL arm, ppc and mips. Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* Merge branch 'next' of ../nextWolfgang Denk2009-12-15-613/+1560
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