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* mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X insteadKumar Gala2007-03-02-5/+5
| | | | | | | | The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all MPC834X class processors. Change the protections from CONFIG_MPC8349 to CONFIG_MPC834X so they are more generic. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: U-Boot support for Wind River SBC8349Paul Gortmaker2007-03-02-0/+4
| | | | | | | | | | | | | | | | | | | | | | | I've redone the SBC8349 support to match git-current, which incorporates all the MPC834x updates from Freescale since the 1.1.6 release, including the DDR changes. I've kept all the SBC8349 files as parallel as possible to the MPC8349EMDS ones for ease of maintenance and to allow for easy inspection of what was changed to support this board. Hence the SBC8349 U-Boot has FDT support and everything else that the MPC8349EMDS has. Fortunately the Freescale updates added support for boards using CS0, but I had to change spd_sdram.c to allow for board specific settings for the sdram_clk_cntl (it is/was hard coded to zero, and that remains the default if the board doesn't specify a value.) Hopefully this should be mergeable as-is and require no whitespace cleanups or similar, but if something doesn't measure up then let me know and I'll fix it. Thanks, Paul.
* mpc83xx: Put the version (and magic) after the HRCW.Jerry Van Baren2007-03-02-12/+16
| | | | | | | Put the version (and magic) after the HRCW. This puts it in a fixed location in flash, not at the start of flash but as close as we can get. Signed-off-by: Jerry Van Baren <vanbaren@cideas.com>
* mpc83xx: Add support for the MPC832XEMDS boardDave Liu2007-03-02-16/+44
| | | | | | This patch supports DUART, ETH3/4 and PCI etc. Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: streamline the 83xx immr head fileDave Liu2007-03-02-12/+12
| | | | | | | | | | | | | | | | For better format and style, I streamlined the 83xx head files, including immap_83xx.h and mpc83xx.h. In the old head files, 1) duplicated macro definition appear in the both files; 2) the structure of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The macro definition put inside the each structure. So, I cleaned up the structure of QE immr from immap_83xx.h, deleted the duplicated stuff and moved the macro definition to mpc83xx.h, Just like MPC8260. CHANGELOG *streamline the 83xx immr head file Signed-off-by: Dave Liu <daveliu@freescale.com>
* Merge with /home/stefan/git/u-boot/denx-merge-srStefan Roese2007-03-01-24/+24
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| * Minor code cleanup.Wolfgang Denk2007-02-27-27/+27
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* | [PATCH] Update AMCC Katmai 440SPe eval board supportStefan Roese2007-03-01-99/+323
|/ | | | | | | | | | | This patch updates the recently added Katmai board support. The biggest change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2 driver. Please note, that still some problems are left with some memory configurations. See the driver for more details. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/denx-merge-srStefan Roese2007-02-20-6/+6
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| * [PATCH 9_9] Use "void *" not "unsigned long *" for block dev read_write ↵Grant Likely2007-02-20-1/+1
| | | | | | | | | | | | | | | | | | buffer pointers Block device read/write is anonymous data; there is no need to use a typed pointer. void * is fine. Also add a hook for block_read functions Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * [PATCH 1_4] Merge common get_dev() routines for block devicesGrant Likely2007-02-20-1/+1
| | | | | | | | | | | | | | Each of the filesystem drivers duplicate the get_dev routine. This change merges them into a single function in part.c Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * Merge with /home/tur/git/u-boot#motionproWolfgang Denk2007-02-16-4/+4
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| | * [Motion-PRO] Preliminary support for the Motion-PRO board.Bartlomiej Sieka2007-02-09-4/+4
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* | | [PATCH] Add support for the AMCC Katmai (440SPe) eval boardStefan Roese2007-02-20-8/+64
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM supportStefan Roese2007-02-20-0/+2943
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the DDR2 controller used on the 440SP and 440SPe. It is tested on the Katmai (440SPe) eval board and works fine with the following DIMM modules: - Corsair CM2X512-5400C4 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM) This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] PPC4xx: Split 4xx SPD SDRAM init routines into 2 filesStefan Roese2007-02-20-413/+478
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the existing 4xx SPD SDRAM initialization routines for the 405 SDRAM controller and the 440 DDR controller don't have much in common this patch splits both drivers into different files. This is in preparation for the 440 DDR2 controller support (440SP/e). Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] PPC4xx: Add support for multiple I2C bussesStefan Roese2007-02-20-213/+245
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for multiple I2C busses on the PPC4xx platforms. Define CONFIG_I2C_MULTI_BUS in the board config file to make use of this feature. It also merges the 405 and 440 i2c header files into one common file 4xx_i2c.h. Also the 4xx i2c reset procedure is reworked since I experienced some problems with the first access on the 440SPe Katmai board. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Correctly display PCI arbiter en-/disabled on some 4xx boardsStefan Roese2007-02-02-6/+10
| | | | | | | | | | | | | | | | Previously the strapping DCR/SDR was read to determine if the internal PCI arbiter is enabled or not. This strapping bit can be overridden, so now the current status is read from the correct DCR/SDR register. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Update 440EPx/440GRx cpu detectionStefan Roese2007-01-31-4/+8
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | LPC2292 SODIMM port coding style cleanup.Wolfgang Denk2007-01-30-5/+5
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* | Add port for the lpc2292sodimm evaluation board from EmbeddedArtistsGary Jennejohn2007-01-24-3/+174
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* Merge with /home/tur/proj/idmr/u-bootWolfgang Denk2007-01-24-1/+33
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| * [ColdFire MCF5271 family] Add CPU detection based on the value of ChipBartlomiej Sieka2007-01-23-1/+33
| | | | | | | | Identification Register (CIR).
* | Merge with /home/hs/SC3/u-boot-devWolfgang Denk2007-01-19-6/+3
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| * | [PATCH] Fix: Compilerwarnings for SC3 board.Heiko Schocher2007-01-18-6/+3
| | | | | | | | | | | | | | | | | | | | | The EBC Configuration Register is now by CFG_EBC_CFG definable Added JFFS2 support for the SC3 board. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | [PATCH] Add support for AMCC Taishan PPC440GX eval boardStefan Roese2007-01-18-76/+104
|/ / | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/hs/SC3/u-bootWolfgang Denk2007-01-15-6/+15
|\ \ | | | | | | | | | Some code cleanup.
| * | Added support for the SOLIDCARD III board from EurodesignHeiko Schocher2007-01-11-2/+7
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Merge with /home/hs/MAN/u-boot-devWolfgang Denk2007-01-15-4/+5
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| * | | [PATCH] Add support for the UC101 board from MAN.Heiko Schocher2006-12-21-4/+5
| | | | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* | | | [PATCH] Fix 440SPe rev B detection from previous patchStefan Roese2007-01-15-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | Merge with git+ssh://sr@pollux.denx.org/home/sr/git/u-boot/denx-merge-srStefan Roese2007-01-13-2/+11
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| * | | | SMC1 uses external CLK4 instead of BRG on spc1920Markus Klotzbuecher2007-01-09-2/+11
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* | | | | [PATCH] Update 440SP(e) cpu revisionsStefan Roese2007-01-13-4/+24
|/ / / / | | | | | | | | | | | | | | | | | | | | Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | [PATCH] 44x: Fix problem with DDR controller setup (refresh rate)Stefan Roese2007-01-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a problem with an incorrect setup for the refresh timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c Signed-off-by: Stefan Roese <sr@denx.de>
* | | | [PATCH] Add DDR2 optimization code for Sequoia (440EPx) boardStefan Roese2007-01-05-3/+0
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge with /home/hs/TQ/u-boot-devWolfgang Denk2006-12-24-3/+64
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| * | Added support for the TQM8272 board from TQHeiko Schocher2006-12-21-3/+64
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Preliminary support for the iDMR board (ColdFire).Bartlomiej Sieka2006-12-20-1/+1
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* | Code cleanup.Wolfgang Denk2006-11-30-11/+11
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* | Merge with http://opensource.freescale.com/pub/scm/u-boot-83xx.gitWolfgang Denk2006-11-30-719/+818
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| * \ Merge http://www.denx.de/git/u-bootKim Phillips2006-11-28-46/+47
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| * | | mpc83xx: Miscellaneous code style fixesTimur Tabi2006-11-28-87/+32
| | | | | | | | | | | | | | | | | | | | | | | | Implement various code style fixes and similar changes. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | mpc83xx: Update 83xx to use fsl_i2c.cTimur Tabi2006-11-03-426/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files. Added multiple I2C bus support to fsl_i2c.c. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | mpc83xx: Replace CFG_IMMRBAR with CFG_IMMRTimur Tabi2006-11-03-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx tree matches the other 8xxx trees. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | mpc83xx: Lindent and clean up cpu/mpc83xx/speed.cKim Phillips2006-11-03-79/+82
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| * | | mpc83xx: Fix the incorrect dcbz operationDave Liu2006-11-03-34/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 834x rev1.x silicon has one CPU5 errata. The issue is when the data cache locked with HID0[DLOCK], the dcbz instruction looks like no-op inst. The right behavior of the data cache is when the data cache Locked with HID0[DLOCK], the dcbz instruction allocates new tags in cache. The 834x rev3.0 and later and 8360 have not this bug inside. So, when 834x rev3.0/8360 are working with ECC, the dcbz instruction will corrupt the stack in cache, the processor will checkstop reset. However, the 834x rev1.x can work with ECC with these code, because the sillicon has this cache bug. The dcbz will not corrupt the stack in cache. Really, it is the fault code running on fault sillicon. This patch fix the incorrect dcbz operation. Instead of CPU FP writing to initialise the ECC. CHANGELOG: * Fix the incorrect dcbz operation instead of CPU FP writing to initialise the ECC memory. Otherwise, it will corrupt the stack in cache, The processor will checkstop reset. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | | mpc83xx: change ft code to modify local-mac-address propertyKim Phillips2006-11-03-2/+2
| | | | | | | | | | | | | | | | | | | | Update 83xx OF code to update local-mac-address properties for ethernet instead of the obsolete 'address' property.
| * | | mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and ↵Timur Tabi2006-11-03-84/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8360EMDS This patch also adds an improved I2C set_speed(), which handles all clock frequencies. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | mpc83xx: add QE ethernet supportDave Liu2006-11-03-7/+120
| | | | | | | | | | | | | | | | this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
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