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* OMAP3: Fix SDRC initNishanth Menon2009-11-27-1/+2
| | | | | | | | | | Defaults are for Infineon DDR timings. Since none of the supported boards currently do XIP boot, these seem to be faulty. fix the values as per the calculations(ACTIMA,B), conf the sdrc power with pwdnen and wakeupproc bits Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP3:SDRC: Cleanup references to SDPNishanth Menon2009-11-27-2/+2
| | | | | | Remove SDP referenced unused defines Signed-off-by: Nishanth Menon <nm@ti.com>
* TI DA8xx: Add DA8xx cpu functionsSekhar Nori2009-11-27-10/+83
| | | | | | | | | | | | Provides initial support for TI OMAP-L1x/DA8xx SoC devices. See http://www.ti.com Provides: Low level initialisation. System clock API. Timer control. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
* TI Davinci timer.c: Remove volatiles and memory mapped structuresNick Thompson2009-11-27-13/+15
| | | | | | | Remove volatiles and memory mapped structure accesses and replace with readl and writel macro usage. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
* Add a unified s3c24x0 header filekevin.morfitt@fearnside-systems.co.uk2009-11-27-47/+19
| | | | | | | | | | This patch adds a unified s3c24x0 cpu header file that selects the header file for the specific s3c24x0 cpu from the SOC and CPU configs defined in board config file. This removes the current chain of s3c24-type #ifdef's from the s3c24x0 code. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* S3C6400/SMDK6400: fix stack_setup in start.SSeunghyeon Rhee2009-11-27-6/+1
| | | | | | | | | | | | | Fix stack_setup to place the stack on the correct address in DRAM accroding to U-Boot standard and remove conditional compilation by CONFIG_MEMORY_UPPER_CODE macro that is not necessry. This macro was introduced and used only by this board for some unclear reason. The definition of this macro is also removed because it's not referenced elsewhere. Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com> Tested-by: Minkyu Kang <mk7.kang@samsung.com>
* s3c64xx: move s3c64xx header files to asm-arm/arch-s3c64xxMinkyu Kang2009-11-27-6/+6
| | | | | | | This patch moves the s3c64xx header files from include/ to include/asm-arm/arch-s3c64xx Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Move s3c24x0 header files to asm-arm/arch-s3c24x0/kevin.morfitt@fearnside-systems.co.uk2009-11-27-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the s3c24x0 header files from include/ to include/asm-arm/arch-s3c24x0/. checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due to a non-UTF8 character in David M?ller's name: ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8 #489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3: + * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch As David's name correctly contains a non-UTF8 character I haven't fixed these errors. The 3 warnings were all because of the use of 'volatile' in s3c24x0.h: WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt #673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35: +typedef volatile u8 S3C24X0_REG8; +typedef volatile u16 S3C24X0_REG16; +typedef volatile u32 S3C24X0_REG32; I'll fix these errors in another patch. Tested by running MAKEALL for ARM8 targets and ensuring there were no new errors or warnings. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ppc4xx: Cleanup PPC4xx I2C infrastructureStefan Roese2009-11-23-102/+97
| | | | | | | | | | | This patch cleans up the PPC4xx I2C intrastructure: - Use C struct to describe the I2C registers instead of defines - Coding style cleanup (braces, whitespace, comments, line length) - Extract common code from i2c_read() and i2c_write() - Remove unneeded IIC defines from ppc405.h & ppc440.h Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove some testing code from 4xx_pcie.cStefan Roese2009-11-23-4/+0
| | | | | | This code got included accidentally. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate pci_master_init() functionStefan Roese2009-11-19-0/+18
| | | | | | | | This patch removes the duplicted implementations of the pci_master_init() function by introducing a weak default function for it. It can be overridden by a board specific version. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate pci_pre_init() functionStefan Roese2009-11-19-23/+104
| | | | | | | | | This patch removes the duplicted implementations of the pci_pre_init() function by introducing a weak default function for it. This weak default has a different implementation for some PPC variants. It can be overridden by a board specific version. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate pci_target_init() functionStefan Roese2009-11-19-0/+106
| | | | | | | | | | This patch removes the duplicted implementations of the pci_target_init() function by introducing a weak default function for it. This weak default has a different implementation for 440EP(x)/GR(x) PPC's. It can be overridden by a board specific version (e.g. PMC440, korat). Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* Merge branch 'master' into nextWolfgang Denk2009-11-15-11/+14
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| * ppc/85xx: Fix how we determine the number of CAM entriesKumar Gala2009-11-13-2/+2
| | | | | | | | | | | | | | | | We were incorrectly use the max CAM size as the number of entries in the array for setting up the addrmap. We should be using the NENTRY field which is the low 12-bits of TLB1CFG. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl-ddr: Fix the chip-select interleaving issueDave Liu2009-11-12-4/+3
| | | | | | | | | | | | | | | | | | | | | | commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3 introduced one new bug to chip-select interleaving. Single DDR controller also can do the chip-select interleaving if there is dual-rank or qual-rank DIMMs. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-11-11-1/+1
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| | * ppc4xx: 44x_spd_ddr2.c: Fix register macro ECCCR -> ECCES (SDRAM_ECCES)Stefan Roese2009-11-09-1/+1
| | | | | | | | | | | | | | | | | | | | | This error only appears when DEBUG is enabled in this driver. That's why it went unnoticed till now. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc/85xx: Fix misc L2 cache enabling bugDave Liu2009-10-31-4/+8
| |/ | | | | | | | | | | | | We need loop-check the flash clear lock and enable bit for L2 cache. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: make boot from NAND full relocation to RAMMingkai Hu2009-11-13-1/+0
| | | | | | | | | | | | | | | | Take advantage of the latest full relocation commit of PPC platform for boot from NAND. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc4xx: Switch to I2C bus numer 0 for chip_config commandStefan Roese2009-11-10-0/+6
| | | | | | | | | | | | | | | | | | All currently available 4xx derivats have the I2C bootstrap EEPROM located on I2C bus number 0. This patch now first sets this bus number, so that the chip_config command also works for board with multiple I2C busses, like Katmai. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Remove duplicated is_pci_host() functionsStefan Roese2009-11-09-0/+20
| | | | | | | | | | | | | | | | | | This patch introduces a weak default function for is_pci_host(), returning 1. This is the default behaviour, since most boards only implement PCI host functionality. This weak default can be overridden by a board specific version if needed. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Consolidate 4xx PCIe board specific configurationStefan Roese2009-11-09-0/+123
| | | | | | | | | | | | | | | | | | This patch consolidates the PPC4xx board specific PCIe configuration code. This way the duplicated code is removed. Boards can implement a special, non standard behaviour (e.g. number of PCIe slots, etc) by overriding the weak default functions. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add common ppc4xx linker scriptStefan Roese2009-11-02-0/+172
|/ | | | | | | | This linker script can be used by all PPC4xx platforms. It works for PPC405 and PPC440 platforms. Boards which need a board specific linker script can override this default linker script in board/*/config.mk. Signed-off-by: Stefan Roese <sr@denx.de>
* Coding Style cleanup; update CHANGELOG, prepare -rc1v2009.11-rc1Wolfgang Denk2009-10-28-31/+29
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+4
| | | | | | | | | | | | | | | | | | eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: MP Boot Page Translation updatePeter Tyser2009-10-27-31/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Fix crashes due to generation of SPE instructionLeon Woestenberg2009-10-26-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot crashed on the last instruction: int parse_stream_outer(struct in_str *inp, int flag) { effa4784: 94 21 ff 38 stwu r1,-200(r1) effa4788: 7c 08 02 a6 mflr r0 effa478c: 42 9f 00 05 bcl- 20,4*cr7+so,effa4790 <parse_stream_outer+0xc> effa4790: 7d 80 00 26 mfcr r12 effa4794: 13 c1 b3 21 evstdd r30,176(r1) ...which is a SPE instruction, although -mno-spe was used. tmp/cross/ppce500v2/bin/powerpc-angstrom-linux-gnuspe-gcc --version powerpc-angstrom-linux-gnuspe-gcc (GCC) 4.3.3 Seems to be a known issue (since 2008-04?!) Googled some, turns out this patch/workaround works for me on MPC8536DS. See http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html for more info Signed-off-by: Leon Woestenberg <leon@sidebranch.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Make L2 support more robustDave Liu2009-10-26-1/+4
| | | | | | | According the user manual, we need loop-check the L2 enable bit set. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master-sync' of git://git.denx.de/u-boot-armWolfgang Denk2009-10-24-854/+1651
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| * arm926ejs: 8-byte align stack to avoid LDRD/STRD problemsSimon Kagstrom2009-10-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | U-boot for Marvell Kirkwood boards no longer work after the EABI changes introduced in commit f772acf8a584067033eff1e231fcd1fb3a00d3d9. This turns out to be caused by a stack alignment issue. The armv5te instructions ldrd/strd instructions require 8-byte alignment to work properly (otherwise undefined behavior). Tested on an OpenRD base board, where both printouts and ubifs stuff now works. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
| * TI OMAP3: make gpmc_config as constNishanth Menon2009-10-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | gpmc_config should not be a variant as it is board specific hence make it a const parameter Fixes issues identified by Dirk: - build issue for zoom2 - warnings for all other OMAP3 platforms using nand/onenand etc Signed-off-by: Nishanth Menon <nm@ti.com>
| * OMAP3: fix warnings when NAND/ONENAND is not usedNishanth Menon2009-10-18-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Fix build warnings by putting specific used variables under required #ifdefs for removing: mem.c:227: warning: unused variable 'f_sec' mem.c:226: warning: unused variable 'f_off' mem.c:225: warning: unused variable 'size' mem.c:224: warning: unused variable 'base' mem.c:222: warning: unused variable 'gpmc_config' Signed-off-by: Nishanth Menon <nm@ti.com>
| * TI: OMAP3: Remove SZ_xx referencesSandeep Paulraj2009-10-18-4/+4
| | | | | | | | | | | | | | This patch removes dependency on the sizes.h header file and removes all references to SZ_xx. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * Clean-up of cpu_arm920t and cpu_arm920t_s3c24x0 codekevin.morfitt@fearnside-systems.co.uk2009-10-13-830/+915
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch re-formats the code in cpu/arm920t and cpu/arm920t/23c24x0 in preparation for changes to add support for the Embest SBC2440-II Board. The changes are as follows: - re-indent the code using Lindent - make sure register layouts are defined using a C struct - replace the upper-case typedef'ed C struct names with lower case non-typedef'ed ones - make sure registers are accessed using the proper accessor functions - run checkpatch.pl and fix any error reports It assumes the following patch has been applied first: - [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009 Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no new warnings or errors were found. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boardskevin.morfitt@fearnside-systems.co.uk2009-10-13-16/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sets CONFIG_SYS_HZ to 1000 for all boards that use the s3c2400 and s3c2410 cpu's which fixes various problems such as the timeouts in tftp being too short. Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no new warnings or errors were found. It was originally submitted on 21/06/2009 but didn't get into the 2009.08 release, and Jean-Pierre made one comment on the original patch (see http://lists.denx.de/pipermail/u-boot/2009-July/055470.html). I've made two changes to the original patch: - it's been re-based to the current release - I've re-named get_timer_raw() to get_ticks() in response to Jean-Pierre's comment This affects the sbc2410, smdk2400, smdk2410 and trab boards. I've copied it directly to the maintainers of all except the sbc2410 which doesn't have an entry in MAINTAINERS. Signed-off-by: Kevin Morfitt <kmorfitt@aselaptop-1.localdomain> Tested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * s5pc1xx: support Samsung s5pc1xx SoCMinkyu Kang2009-10-13-0/+703
| | | | | | | | | | | | | | | | This patch adds support for the Samsung s5pc100 and s5pc110 SoCs. The s5pc1xx SoC is an ARM Cortex A8 processor. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-10-24-3/+85
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| * | ppc4xx: Print PCI synchronous clock frequency upon bootupStefan Roese2009-10-23-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | Some 4xx variants (e.g. 440EP(x)/GR(x)) have an internal synchronous PCI clock. Knowledge about the currently configured value might be helpful. So let's print it out upon bootup. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Add function to check and dynamically change PCI sync clockStefan Roese2009-10-23-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPC440EP(x)/PPC440GR(x): In asynchronous PCI mode, the synchronous PCI clock must meet certain requirements. The following equation describes the relationship that must be maintained between the asynchronous PCI clock and synchronous PCI clock. Select an appropriate PCI:PLB ratio to maintain the relationship: AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz This patch now adds a function to check and reconfigure the sync PCI clock to meet this requirement. This is in preparation for some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this function to not violate the PCI clocking rules. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Update flash size in reg property of the NOR flash nodeStefan Roese2009-10-23-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Till now only the ranges in the ebc node are updated with the values currently configured in the PPC4xx EBC controller. With this patch now the NOR flash size is updated in the device tree blob as well. This is done by scanning the compatible nodes "cfi-flash" and "jedec-flash" for the correct chip select number. This size fixup is enabled for all AMCC eval board right now. Other 4xx boards may want to enable it as well, if this problem with multiple NOR FLASH sizes exists. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | cpu/ppc4xx/fdt.c: avoid strcpy() to constant stringWolfgang Denk2009-10-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | strcpy() was iused with the target address being a pointer to a constant string, which potentially is read-only. Use a (writable) array of characters instead. Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2009-10-24-0/+39
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| * | mpc83xx: mpc8313 - handle erratum IPIC1 (TSEC IRQ number swappage)Kim Phillips2009-10-16-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1 h/w (see AN3545). The base device tree in use has rev. 1 ID numbers, so if on Rev. 2 (and higher) h/w, we fix them up here. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Reviewed-by: Roland Lezuo <roland.lezuo@chello.at>
* | | mpc8xxx: improve LAW error messages when setting up DDRPaul Gortmaker2009-10-16-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When setting up the LAWs for the DDR, if there was an error, you got the not-so-helpful error text "ERROR" and nothing else. Not only is it non-informative, but it is also pretty frustrating trying to grep for "ERROR" in the source. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2009-10-15-0/+3
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| * | Blackfin: reset watchdog in udelay()Mike Frysinger2009-10-13-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | All arches apparently should reset the watchdog in their udelay loop as noted on the mailing list recently: > A comment in flash_status_check() suggests that udelay() is > expected to reset the watchdog, but I can't find any architecture > where it does. If this is missing in other architectures, it should be fixed at the root cause, i. e. in udelay() or in the respective support routines. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | arm: Correct build with CONFIG_SYS_HUSH_PARSER setSimon Kagstrom2009-10-13-0/+1
| | | | | | | | | | | | | | FLAG_PARSE_SEMICOLON is not defined without hush.h, so include that. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* | Add support for Eukrea CPU9260/CPU9G20 SBCTom Rix2009-10-13-1/+2
| | | | | | | | | | | | | | | | | | these boards are built around Atmel's AT91SAM9260/9G20 and have up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND and include a 10/100 Ethernet PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* | Add support for Eukrea CPUAT91 SBCTom Rix2009-10-13-2/+252
| | | | | | | | | | | | | | | | | | CPUAT91 is built around Atmel's AT91RM9200 and has up to 16MB of NOR flash, up to 128MB of SDRAM, and includes a Micrel KS8721 PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
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