summaryrefslogtreecommitdiff
path: root/cpu
Commit message (Collapse)AuthorAgeLines
* Merge: Add support for AMCC 440SPe CPU based eval board (Yucca).Marian Balakowicz2006-06-30-70/+623
|\
| * Add support for AMCC 440SPe CPU based eval board (Yucca).Marian Balakowicz2006-06-30-70/+623
| |
* | Add support for wrPPMC7xx/74xx boardsHeiko Schocher2006-06-19-2/+4
| | | | | | | | Patch from Richard Danter, 12 Aug 2005
* | Merge with ssh://fifi/home/wd/git/u-boot/masterWolfgang Denk2006-06-19-11/+172
|\ \
| * | Add support for CONFIG_SERIAL_MULTI on MPC5xxxWolfgang Denk2006-06-16-10/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Martin Krause, 8 Jun 2006 This patch supports two serial consoles on boards with a MPC5xxx CPU. The console can be switched at runtime by setting stdin, stdout and stderr to the desired serial interface (serial0 or serial1). The PSCs to be used as console port are definded by CONFIG_PSC_CONSOLE and CONFIG_PSC_CONSOLE2. See README.serial_multi for details.
| * | Bugfix in I2C initialisation on S3C2400.Wolfgang Denk2006-06-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | If the bus is blocked because of a previously interrupted transfer, up to eleven clocks are generated on the I2CSCL line to complete the transfer and to free the bus. With this fix pin I2CSCL (PG6) is really configured as GPIO so the clock pulses are really generated. Patch by Martin Krause, 04 Apr 2006
* | | Fix IxEthDB.h to compile againStefan Roese2006-06-14-2/+2
| | | | | | | | | | | | Patch by Stefan Roese, 14 Jun 2006
* | | Minor cleanup for PCS440EP boardStefan Roese2006-06-13-1/+1
|/ / | | | | | | Patch by Stefan Roese, 13 Jun 2006
* | Minor code cleanup.Wolfgang Denk2006-06-10-4/+4
| |
* | Merge with /home/hs/U-Boot/u-boot-devWolfgang Denk2006-06-10-57/+353
|\ \
| * | * Add EPCS Controller bootrom work-around for Nios-IIHeiko Schocher2006-04-20-0/+15
| | | | | | | | | | | | | | | | | | | | | Patch from Scott McNutt 11, Aug 2005 -When booting from an epcs controller, the epcs bootrom may leave the slave select in an asserted state causing soft reset hang. This patch ensures slave select is negated at reset.
| * | Fix I/O Macros and mini-app stubs for Nios-IIHeiko Schocher2006-04-20-37/+44
| | | | | | | | | | | | | | | | | | | | | | | | Patch by Scott McNutt 11, Aug 2005 -Fix asm/io.h macros -Eliminate use of CACHE_BYPASS in cpu code -Eliminate assembler warnings -Fix mini-app stubs and force no small data
| * | Add MCF5282 support (without preloader)Heiko Schocher2006-04-20-32/+334
| | | | | | | | | | | | | | | | | | | | | | | | relocate ichache_State to ram u-boot can run from internal flash Add EB+MCF-EV123 board support. Add m68k Boards to MAKEALL Patch from Jens Scharsig, 08 Aug 2005
* | | Nios II - Add EPCS Controller bootrom work-aroundScott McNutt2006-06-08-0/+15
| | | | | | | | | | | | | | | | | | | | | -When booting from an epcs controller, the epcs bootrom may leave the slave select in an asserted state causing soft reset hang. This patch ensures slave select is negated at reset. Patch by Scott McNutt, 08 Jun 2006
* | | Nios II - Fix I/O Macros and mini-app stubsScott McNutt2006-06-08-37/+44
| | | | | | | | | | | | | | | | | | | | | | | | -Fix asm/io.h macros -Eliminate use of CACHE_BYPASS in cpu code -Eliminate assembler warnings -Fix mini-app stubs and force no small data Patch by Scott McNutt, 08 Jun 2006
* | | Add support for PCS440EP boardStefan Roese2006-06-02-2/+127
| | | | | | | | | | | | Patch by Stefan Roese, 02 Jun 2006
* | | Fix PCI to memory window size problems on PM82x boardsWolfgang Denk2006-05-30-2/+2
| | | | | | | | | | | | | | | | | | We use the "automatic" mode that was used for the MPC8266ADS and MPC8272 boards. Eventually this should be used on all boards?] Patch by Wolfgang Grandegger, 17 Jan 2006
* | | Minor cleanup.Wolfgang Denk2006-05-30-2590/+74
| | |
* | | * Update Intel IXP4xx supportWolfgang Denk2006-05-30-15/+72222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add IXP4xx NPE ethernet MAC support - Add support for Intel IXDPG425 board - Add support for Prodrive PDNB3 board - Add IRQ support Patch by Stefan Roese, 23 May 2006 [This patch does not include cpu/ixp/npe/IxNpeMicrocode.c which still sufferes from licensing issues. Blame Intel.]
* | | Fix problem in PVR detection for 440GRStefan Roese2006-05-18-1/+1
| | | | | | | | | | | | Patch by Stefan Roese, 18 May 2006
* | | Minor cleanup.Wolfgang Denk2006-05-10-27/+26
| | |
* | | Add support for AMCC 440EP Rev C and 440GR Rev BStefan Roese2006-05-10-1/+9
| | | | | | | | | | | | Patch by John Otken, 08 May 2006
* | | Update omap5912osk board supportStefan Roese2006-05-10-1/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Fix OMAP support that omap5912osk compiles in current source tree - Update with code from "http://omap.spectrumdigital.com/osk5912" to fix problems with DDR initialization - Fix timer setup - Use CFI flash driver and support complete 32MB of onboard flash - Add "print_cpuinfo()" and "checkboard()" functions to display CPU (with frequency) and Board infos Patch by Stefan Roese, 10 May 2006
* | | Fix watchdog issues for ColdFire boards.Wolfgang Denk2006-05-09-1/+4
| | |
* | | Merge with /home/m8/git/u-bootWolfgang Denk2006-05-09-15/+172
|\ \ \
| * | | Make R5200 specific low level initialization board conditional.Marian Balakowicz2006-05-09-9/+15
| | | |
| * | | Update CPU target identification strings for Coldfire family.Marian Balakowicz2006-05-09-6/+7
| | | |
| * | | Fix serial console support for MCF5271.Marian Balakowicz2006-05-09-6/+16
| | | |
| * | | Add support for Freescale M5271: Merge with /work/u-boot.mcf5271Marian Balakowicz2006-04-27-4/+144
| |\ \ \ | | |/ / | |/| |
| | * | Add support for Freescale M5271 processorZachary P. Landau2006-01-26-4/+144
| | |/
* | | Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port:Kumar Gala2006-04-20-1/+1
|/ / | | | | | | | | | | | | | | | | - Removed MPC8349ADS port - Added PCI support to MPC8349ADS - reworked memory map to allow mapping of all regions with BATs Patch by Kumar Gala 20 Apr 2006 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | MPC5200: enable snooping of DMA transactions on XLB even if no PCIWolfgang Denk2006-04-18-4/+4
| | | | | | | | | | is configured; othrwise DMA accesses aren't cache coherent which causes for example USB to fail.
* | Some code cleanupWolfgang Denk2006-04-16-111/+111
| |
* | Fix Lite500B support: Merge with /home/raj/git/u-boot.l5200b_pciWolfgang Denk2006-04-06-5/+5
|\ \
| * | Set SDelay register in the DDR controller for the MPC5200B chip.Rafal Jaworowski2006-03-29-5/+5
| | |
* | | Merge with /home/sr/git/u-boot/4xx-sdramWolfgang Denk2006-04-05-34/+342
|\ \ \
| * | | Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)Stefan Roese2006-03-31-34/+342
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 405 SDRAM: - The SDRAM parameters can now be defined in the board config file and the 405 SDRAM controller values will be calculated upon bootup (see PPChameleonEVB). When those settings are not defined in the board config file, the register setup will be as it is now, so this implementation should not break any current design using this code. Thanks to Andrea Marson from DAVE for this patch. 440 DDR: - Added function sdram_tr1_set to auto calculate the TR1 value for the DDR. - Added ECC support (see p3p440). Patch by Stefan Roese, 17 Mar 2006
* | | Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.SWolfgang Denk2006-04-03-1/+2
| | | | | | | | | | | | Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473]
* | | GCC-4.x fixes: clean up global data pointer initialization for all boards.Wolfgang Denk2006-03-31-233/+195
| | |
* | | Merge with http://www.denx.de/git/u-boot.gitMarkus Klotzbuecher2006-03-24-453/+4384
|\ \ \ | |/ /
| * | Add support for MPC859/866 Rev. A.0Wolfgang Denk2006-03-18-3/+8
| | |
| * | Support for DDR with 32-data path. Addotional notes on injectingRafal Jaworowski2006-03-16-12/+49
| | | | | | | | | | | | multiple-bit errors.
| * | Add support for ECC DDR initialization on MPC83xx.Marian Balakowicz2006-03-14-22/+108
| | |
| * | Add DMA support for MPC83xx.Marian Balakowicz2006-03-14-0/+85
| | |
| * | Add sync in do_reset() routine for MPC83xx after RPR registerMarian Balakowicz2006-03-14-0/+2
| | | | | | | | | | | | | | | was written to. It is need on some targets when BAT translation is enabled.
| * | Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.Marian Balakowicz2006-03-14-0/+34
| | |
| * | Correct shift offsets in icache_status and dcache_status for MPC83xx.Marian Balakowicz2006-03-14-2/+2
| | |
| * | Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific timer andWolfgang Denk2006-03-13-167/+531
| | | | | | | | | | | | | | | cpu_reset code from cpu/$(CPU) into the new cpu/$(CPU)/$(SOC) directories Patch by Andreas Engel, 13 Mar 2006
| * | Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.cStefan Roese2006-03-13-1/+1
| | | | | | | | | | | | Patch by Stefan Roese, 13 Mar 2006
| * | cpu/ppc4xx/start.S : exceptions are enabled after relocationStefan Roese2006-03-13-23/+18
| | | | | | | | | | | | Patch by Cedric Vincent, 6 June 2005
generated by cgit v1.1 at 2024-12-26 04:19:41 +0000