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* davinci: add basic dm355/dm350/dm335 supportDavid Brownell2009-06-12-0/+46
| | | | | | | | | | | | | Add some basic declarations for DaVinci DM355/DM350/DM335 support, keyed on CONFIG_SOC_DM355. (DM35X isn't quite right because the DM357 is very different; while the DM355 is like a DM355 without the MPEG/JPEG coprocessor). These have different peripherals than the DM6446, and some of the peripherals are at different addresses. Notably for U-Boot, there's no EMAC, and the NAND controller address is different Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* davinci: fix dm644x bugletsDavid Brownell2009-06-12-1/+3
| | | | | | | | Fix two buglets in the dm644x support: don't set two must-be-zero bits in the UART management register; and only include the I2C hooks if the I2C driver is being included. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* davinci: split out some dm644x-specific bits from pscDavid Brownell2009-06-12-75/+123
| | | | | | | | | | | | | | Split out DaVinci DM6446-specific bits from more generic bits: - Add a CONFIG_SOC_DM644X. All current boards use DM6446 chips; DM6443 and DM6441 chips differ in available peripherals. - Move most DM644X-specific bits from psc.c to a new dm644x.c file, which is conditionally built. It provides device-specific setup. Plus minor coding style and comment updates with respect to the PSC. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* davinci: cpu-specific build uses conditional make syntaxDavid Brownell2009-06-12-3/+5
| | | | | | | | | | | Update cpu/arm926ejs/davinci/Makefile to use COBJ-y type syntax. Add the first conditional: for EMAC driver support. Not all chips have an EMAC; and boards might not use it, anyway. This doesn't touch PHY configuration; that should eventually become conditional too. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* davinci: move psc support board-->cpuDavid Brownell2009-06-12-1/+183
| | | | | | | | Move DaVinci PSC support from board/* to cpu/* where it belongs. The PSC module manages clocks and resets for all DaVinci-family SoCs, and isn't at all board-specific. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* DaVinci now respects SKIP_LOWLEVEL_INITDavid Brownell2009-06-12-1/+5
| | | | | | | | Don't needlessly include lowlevel init code; that's only really needed with boot-from NOR (not boot-from-NAND). The 2nd stage loader (UBL) handles that before it loads U-Boot. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ppc4xx: Add Sequoia RAM-booting targetStefan Roese2009-06-12-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds another build target for the AMCC Sequoia PPC440EPx eval board. This RAM-booting version is targeted for boards without NOR FLASH (NAND booting) which need a possibility to initially program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000) configured to setup the SDRAM, this debugger can load this RAM- booting image to the target address in SDRAM (in this case 0x1000000) and start it there. Then U-Boot's standard NAND commands can be used to program the NAND FLASH (e.g. "nand write ..."). Here the commands to load and start this image from the BDI2000: 440EPX>reset halt 440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin 440EPX>go 0x1000000 Please note that this image automatically scans for an already initialized SDRAM TLB (detected by EPN=0). This TLB will not be cleared. This TLB doesn't need to be TLB #0, this RAM-booting version will detect it and preserve it. So booting via BDI2000 will work and booting with a complete different TLB init via U-Boot works as well. Signed-off-by: Stefan Roese <sr@denx.de>
* i2c: Create common default i2c_[set|get]_bus_speed() functionsPeter Tyser2009-06-12-51/+0
| | | | | | | | | | | | | New default, weak i2c_get_bus_speed() and i2c_set_bus_speed() functions replace a number of architecture-specific implementations. Also, providing default functions will allow all boards to enable CONFIG_I2C_CMD_TREE. This was previously not possible since the tree-form of the i2c command provides the ability to display and modify the i2c bus speed which requires i2c_[set|get]_bus_speed() to be present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* i2c.h: Provide a default CONFIG_SYS_I2C_SLAVE valuePeter Tyser2009-06-12-11/+0
| | | | | | | | Many boards/controllers/drivers don't support an I2C slave interface, however CONFIG_SYS_I2C_SLAVE is used in common code so provide a default Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BITKumar Gala2009-06-12-39/+41
| | | | | | | | | | | | | | | The ddr code computes most things as 64-bit quantities and had some places in the middle that it was using phy_addr_t and phys_size_t. Instead we use unsigned long long through out and only at the last stage of setting the LAWs and reporting the amount of memory to the board code do we truncate down to what we can cover via phys_size_t. This has the added benefit that the DDR controller itself is always setup the same way regardless of how much memory we have. Its only the LAW setup that limits what is visible to the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Use print_size to report amount of memory not mapped by TLBsKumar Gala2009-06-12-1/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* at91/cpu.c: add missing Copyright & GPL headerJean-Christophe PLAGNIOL-VILLARD2009-06-10-0/+23
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* 85xx: bugfix for reading maximum TLB size on mpc85xxFredrik Arnerup2009-06-09-1/+1
| | | | | | | | | | | | | The MAXSIZE field in the TLB1CFG register is 4 bits, not 8 bits. This made setup_ddr_tlbs() try to set up a TLB larger than the e500 maximum (256 MB) which made u-boot hang in board_init_f() when trying to create a new stack in RAM. I have an mpc8540 with one 1GB dimm. Signed-off-by: Fredrik Arnerup <fredrik.arnerup@edgeware.tv> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* ppc4xx: Fix problem with ECC ordering for PPC4xx NDFC platformsStefan Roese2009-05-23-2/+2
| | | | | | | | | | | | | This patch now uses the correct ECC byte order (Smart Media - SMC) to be used on the 4xx NAND FLASH driver. Without this patch we have incompatible ECC byte ordering to the Linux kernel NDFC driver. Please note that we also have to enable CONFIG_MTD_NAND_ECC_SMC in drivers/mtd/nand/nand_ecc.c for correct operation. This is done with a seperate patch. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* ppc4xx: Move definition for PPC4xx NAND FLASH controller to headerStefan Roese2009-05-23-6/+3
| | | | | | | | | This patch moves the definition for the PPC4xx NAND FLASH controller (NDFC) CONFIG_NAND_NDFC into include/ppc4xx.h. This is needed for the upcoming fix for the ECC byte ordering of the NDFC driver. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* Blackfin: fix timer_init()/timer_reset()Graf Yang2009-05-19-2/+3
| | | | | | | | | | | | | The timer_init() function was not using the right csync instruction, nor was it doing it right after disabling the core timer. The timer_reset() function would reset the timestamp, but not the actual timer, so there was a common edge case where get_timer() return a jump of one timestamp (couple milliseconds) right after resetting. This caused many functions to improperly timeout right away. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* MIPS: Implement ethernet halt for au1x00Thomas Lange2009-05-16-0/+4
| | | | | | | | | Implement ethernet halt() by putting MAC0 in reset. If we do not do this, we will get memory corruption when ethernet frames are received during early OS boot. Signed-off-by: Thomas Lange <thomas@corelatus.se> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* 74xx_7xx: Fix rounding problem in CPU frequency calculationStefan Roese2009-05-15-2/+2
| | | | | | | This patch fixes a problem in the CPU frequency calculation. Without it a 798MHz CPU is displayed as 368.503 MHz. And with it it's 798 MHz. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix e-mail address of Gary Jennejohn.Detlev Zundel2009-05-15-51/+51
| | | | Signed-off-by: Detlev Zundel <dzu@denx.de>
* MPC8260: fixup device tree by property instead of pathWolfgang Denk2009-05-15-5/+6
| | | | | | | | | | | | | | | | | | | | cpu/mpc8260/cpu.c used to use do_fixup_by_path_u32() to update the clock frequencies in the device tree, using a CPU path "/cpus/OF_CPU", with OF_CPU beind defined in the board config file. However, this does not work when one board config file (here: MPC8260ADS.h) is intended to be used for several diffrent CPUs and therefor contains a generic definition like "cpu@0", as the device trees that will then be loaded will contain specific names like "PowerPC,8272@0". We switch to using do_fixup_by_prop_u32() instead, so we can search for device_type="cpu", as it is done in other architectures, too. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* AFEB9260 network fixSergey Lapin2009-05-13-1/+1
| | | | | | | | AFEB9260 uses PA10, PA11 for ETX2 and ETX3. Also, due to extarnal pull-up on IRQ line, Micrel PHY ID is 1 after reset sequence, not 0. Signed-off-by: Sergey Lapin <slapin@ossfans.org>
* Blackfin: avoid get_sclk() with early serial debugMike Frysinger2009-05-06-5/+5
| | | | | | | | When the clock functions were changed to use cached values (and thereby avoiding expensive math functions), early serial debug broke because the baud programming is called before external memory is available. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: fix booting with older bootroms (no EVT1)Mike Frysinger2009-05-06-1/+11
| | | | | | | | | | | When dropping jump block support, the assumption was that all bootroms supported entry point redirection via the EVT1 register. Unfortunately, this turned out to be incorrect for the oldest Blackfin parts (BF533-0.2 and older and BF561). No one really noticed earlier because these parts usually are booted by bypassing the bootrom entirely, and older BF533 parts are not supported at all (too many anomalies). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: recurse with early serial initcodeMike Frysinger2009-05-06-1/+1
| | | | | | | Make sure we recurse through serial_putc() rather than bang on the UART transmit register directly to avoid hardware overflows when using \n. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* at91: remove lowlevel_init.SJean-Christophe PLAGNIOL-VILLARD2009-05-01-61/+2
| | | | | | | | | | | | lowlevel_init.S is not used any more so remove it. As consequence, we also don't have to generate u-boot.lds but can use a static version as before. This also fixes the out-of-tree build problem introduced with commit f0a2c7b4 "at91: add support for the PM9263 board" Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Update CHANGELOG; minor coding style cleanup.Wolfgang Denk2009-05-01-2/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* OMAP3: Fix timer handling to 1ms and CONFIG_SYS_HZ to 1000Manikandan Pillai2009-04-30-59/+28
| | | | | Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Manikandan Pillai <mani.pillai@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-04-30-151/+122
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| * at91: fixed plla calc when no USB support is activeDaniel Gorsulowski2009-04-29-1/+1
| | | | | | | | | | Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * arm925t: Fix CONFIG_SYS_HZ to 1000Ladislav Michl2009-04-29-64/+24
| | | | | | | | | | | | | | | | | | | | | | Let CONFIG_SYS_HZ to have value of 1000 effectively fixing all users of get_timer. Changes since original version: * Set PTV=2 (divisor 8) for boards using 12MHz timer clock source to improve timer resolution. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
| * OMAP3: Print correct silicon revisionSanjeev Premi2009-04-29-11/+27
| | | | | | | | | | | | | | | | | | | | The function display_board_info() displays incorrect silicon revision - based on the return value from function get_cpu_rev(). This patch fixes the problem. Signed-off-by: Sanjeev Premi <premi@ti.com>
| * OMAP3: Remove unused board-typesSanjeev Premi2009-04-29-17/+0
| | | | | | | | | | | | | | | | | | | | | | The board-types defined in struct omap3_sysinfo seem to be unused. The function display_board_info() is passed board type as an argument; which is ignored. This patch removes all uses of board-type, related definitions and functions. Signed-off-by: Sanjeev Premi <premi@ti.com>
| * OMAP3: Use functions print_cpuinfo() and checkboard()Sanjeev Premi2009-04-29-60/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the functions print_cpuinfo() and checkboard() to display the cpu and board specific information. These functions reuse content from the existing function display_board_info() - which has been removed. Also, updated the existig OMAP3 configurations to define: - CONFIG_DISPLAY_CPUINFO - CONFIG_DISPLAY_BOARDINFO Signed-off-by: Sanjeev Premi <premi@ti.com>
* | Replace __asm references with __asm__Peter Tyser2009-04-28-1/+1
| | | | | | | | | | | | | | | | __asm__ follows gcc's documented syntax and is generally more common than __asm. This change is only asthetic and should not affect functionality. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | Replace __attribute references with __attribute__Peter Tyser2009-04-28-19/+20
| | | | | | | | | | | | | | | | __attribute__ follows gcc's documented syntax and is generally more common than __attribute. This change is only asthetic and should not affect functionality. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2009-04-27-2/+2
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| * 83xx: searching "muram-data" by compatible propertyHeiko Schocher2009-04-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | if using CONFIG_BOOTCOUNT_LIMIT feature on a MPC8360 CPU in the muram-data node, the reg entry needs to be updated. This is done in fdt_fixup_muram(), but we should use the compatible "fsl,qe-muram-data" for searching the node instead of searching the muram-data node with an absolute path. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-at91Wolfgang Denk2009-04-24-42/+276
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| * at91sam9/at91cap: fix CONFIG_SYS_HZ to 1000Jean-Christophe PLAGNIOL-VILLARD2009-04-16-38/+44
| | | | | | | | | | | | | | | | The timer has been rewrote with a precision at ~0,18% Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Tested-by: Sergey Lapin <slapin@ossfans.org> Tested-by: Eric BENARD <ebenard@free.fr>
| * at91: add support for the PM9263 board of Ronetix GmbHIlko Iliev2009-04-16-4/+14
| | | | | | | | | | | | | | | | | | | | The PM9263 board is based on the AT91SAM9263-EK board. Here is the page on Ronetix website: http://www.ronetix.at/starter_kit_9263.html Signed-off-by: Ilko Iliev <iliev@ronetix.at> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * at91sam9/at91cap: improve clock frameworkJean-Christophe PLAGNIOL-VILLARD2009-04-16-0/+218
| | | | | | | | | | | | calculate dynamically the clock rate and pllb setting for usb Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ppc4xx: Add "booting from NAND" to 4xx NAND-booting targetsStefan Roese2009-04-16-1/+5
|/ | | | | | | | This additional text in the bootup log helps to see if the board is configured for NAND-booting. Especially helpful for boards that can boot from NOR and NAND (e.g. most of the AMCC eval boards). Signed-off-by: Stefan Roese <sr@denx.de>
* Blackfin: audit UART for all known anomaliesMike Frysinger2009-04-06-2/+21
| | | | | | | There is no code change here, just new comments, but this keeps me from having to do another audit from scratch in the future. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: add check for anomaly 05000362Mike Frysinger2009-04-06-0/+9
| | | | | | | | | | | | | | | DESCRIPTION: The column address width settings for banks 2 and 3 are misconnected in the SDRAM controller. Accesses to bank 2 will result in an error if the Column Address Width for bank 3 (EB3CAW ) is not set to be the same as that of bank 2. WORKAROUND: If using bank 2, make sure that banks 2 and 3 have the same column address width settings in the EBIU_SDBCTL register. This must be the case regardless of whether or not bank 3 is enabled. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: add comment about anomaly 05000430 avoidanceMike Frysinger2009-04-06-0/+2
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: add workaround for anomaly 05000242Mike Frysinger2009-04-06-1/+1
| | | | | | | | | | | | | DESCRIPTION: If the DF bit is set prior to a hardware reset, the PLL will continue to divide CLKIN by 2 after the hardware reset, but the DF bit itself will be cleared in the PLL_CTL register. WORKAROUND: Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by 2 after reset. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: add workaround for anomaly 05000171Mike Frysinger2009-04-06-0/+4
| | | | | | | | | | | | | DESCRIPTION: The Boot ROM is executed at power up/reset and changes the value of the SICA_IWR registers from their default reset value of 0xFFFF, but does not restore them. WORKAROUND: User code should not rely on the default value of these registers. Set the desired values explicitly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-04-05-1142/+108
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| * arm: unify reset commandJean-Christophe PLAGNIOL-VILLARD2009-04-05-131/+0
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * arm: clean cache managementJean-Christophe PLAGNIOL-VILLARD2009-04-05-620/+103
| | | | | | | | | | | | unify arm cache management except for non standard cache as ARM7TDMI Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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