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* ppc4xx: PPC440EPx Emit DDR0 registers on machine check interruptNiklaus Giger2007-06-25-1/+86
| | | | | | | | | | | | This patch prints the DDR status registers upon machine check interrupt on the 440EPx/GRx. This can be useful especially when ECC support is enabled. I added some small changes to the original patch from Niklaus to make it compile clean. Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix O=buildir buildsNiklaus Giger2007-06-25-1/+1
| | | | | | | | This patch fixes the problem to assemble cpu/ppc4xx/start.S experienced last week where building failed having specified O=../build.sequoia. Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
* ppc4xx: Add pci_pre_init() for 405 boardsMatthias Fuchs2007-06-25-8/+22
| | | | | | | | | | | | | This patch adds support for calling a plattform dependant pci_pre_init() function for 405 boards. This can be used to move the current pci_405gp_fixup_irq() function into the board code. This patch also makes the CFG_PCI_PRE_INIT define obsolete. A default function with 'weak' attribute is used when a board specific pci_pre_init() is not implemented. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* ppc4xx: Fix problem with extended program_tlb() funtionStefan Roese2007-06-22-0/+8
| | | | | | | | | The recently extended program_tlb() function had a problem when multiple TLB's had to be setup (for example with 512MB of SDRAM). The virtual address was not incremented. This patch fixes this issue and is tested on Katmai with 512MB SDRAM. Signed-off-by: Stefan Roese <sr@denx.de>
* [ppc] Fix build breakage for all non-4xx PowerPC variants.Rafal Jaworowski2007-06-22-21/+20
| | | | | - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup
* Coding style cleanup. Refresh CHANGELOG.Wolfgang Denk2007-06-20-138/+137
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* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-06-20-1/+1
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| * Fix config problems on SC3 board; make ide_reset_timeout work.Wolfgang Denk2007-06-08-1/+1
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* | [ppc4xx] Fix problem with NAND booting on AMCC AcadiaStefan Roese2007-06-19-3/+3
| | | | | | | | | | | | | | | | The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/stefan/git/u-boot/denx-440-exceptionsStefan Roese2007-06-15-204/+242
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| * | ppc4xx: Clean up 440 exceptions handlingGrzegorz Bernacki2007-06-15-204/+242
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Introduced dedicated switches for building 440 and 405 images required for 440-specific machine instructions like 'rfmci' etc. - Exception vectors moved to the proper location (_start moved away from the critical exception handler space, which it occupied) - CriticalInput now serviced (with default handler) - MachineCheck properly serviced (added a dedicated handler and return subroutine) - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, unhandled and those not relevant for 4xx were eliminated) - Eliminated Linux leftovers, removed dead code Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Signed-off-by: Rafal Jaworowski <raj@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | [ppc4xx] Extend 44x GPIO setup with default output stateStefan Roese2007-06-15-0/+38
| | | | | | | | | | | | | | The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup is extended with the default GPIO output state (level). Signed-off-by: Stefan Roese <sr@denx.de>
* | [ppc4xx] Extend program_tlb() with virtual & physical addressesStefan Roese2007-06-14-37/+48
| | | | | | | | | | | | | | | | | | Now program_tlb() allows to program a TLB (or multiple) with different virtual and physical addresses. With this change, now one physical region (e.g. SDRAM) can be mapped 2 times, once with caches diabled and once with caches enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] fix gpio setting when using CFG_440_GPIO_TABLEBenoît Monin2007-06-08-2/+2
|/ | | | | | | | Set the correct value in GPIOx_TCR when configuring the gpio with CFG_440_GPIO_TABLE. Signed-off-by: Benoit Monin <bmonin@adeneo.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/wd/git/u-boot/custodian/u-boot-mpc86xxWolfgang Denk2007-06-06-2/+0
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| * Merge branch 'mpc8641'Jon Loeliger2007-06-05-2/+0
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| | * mpc8641 image size cleanupEd Swarthout2007-06-05-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | e600 does not have a bootpg restriction. Move the version string to beginning of image at fff00000. Resetvec.S is not needed. Update flash copy instructions. Add tftpflash env variable Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | | Merge with /home/wd/git/u-boot/custodian/u-boot-armWolfgang Denk2007-06-06-0/+765
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| * \ \ Merge with git://www.denx.de/git/u-boot.gitPeter Pearse2007-05-18-279/+378
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| * | | | Add the files for the SMN42 boardPeter Pearse2007-05-09-0/+765
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* | | | ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval boardStefan Roese2007-06-06-17/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
* | | | [PATCH] Fix ppc4xx bootstrap letter displayed on startupBenoît Monin2007-06-04-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The attached patch is mainly cosmetic, allowing u-boot to display the correct bootstrap option letter according to the datasheets. The original patch was extended with 405EZ support by Stefan Roese. Signed-off-by: Benoit Monin <bmonin@adeneo.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* | | | Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese2007-06-01-287/+349
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| * | | | ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval boardStefan Roese2007-06-01-92/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | NAND: Add hardware ECC support to the PPC4xx NAND driver ndfc.cStefan Roese2007-06-01-20/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds hardware ECC support to the NDFC driver. It also changes the register access from using the "simple" in32/out32 functions to the in_be32/out_be32 functions, which make sure that the access is correctly synced. This is the only recommended access to SoC registers in the current Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: 44x DDR driver code cleanup and small fix for BambooStefan Roese2007-06-01-175/+166
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)Stefan Roese2007-06-01-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add config option for 180 degree advance clock control as needed for the AMCC Luan eval board. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | Merge with /home/tur/git/u-boot#motionproWolfgang Denk2007-05-28-8/+4
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| * | | | | MPC5XXX, Motion-PRO: Fix PHY initialization problem.Bartlomiej Sieka2007-05-27-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which networking does not function. This commit switches PHY to TX mode by clearing the FX_SEL bit of Mode Control Register. It also reverses commit 008861a2f3ef2c062744d733787c7e530a1b8761, i.e., a temporary workaround. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
| * | | | | MPC5xxx: Change names of defines related to IPB and PCI clocks.Bartlomiej Sieka2007-05-27-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining them does not cause PCI or IPB clocks to run at the specified speed. Instead, they configure divisors used to calculate said clocks. This patch renames the defines according to their real function. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
* | | | | | ppc4xx: Add 405 support to 4xx NAND driver ndfc.cStefan Roese2007-05-22-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for 405 PPC's to the 4xx NAND driver ndfc.c. This is in preparation for the new AMCC 405EZ. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | ppc4xx: Fix problem in 405EZ OCM initializationStefan Roese2007-05-21-1/+1
| |_|_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | As spotted by Bruce Adler this patch fixes an initialization problem for the 405EZ OCM. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xxWolfgang Denk2007-05-16-43/+279
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| * | | | | Fix memory initialization on MPC8349E-mITXTimur Tabi2007-05-01-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Michael Benedict <MBenedict@twacs.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | | | mpc83xx: replace elaborate boottime verbosity with 'clocks' commandKim Phillips2007-05-01-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and fix CPU: to align with Board: display text. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | | | mpc83xx: minor fixups for 8313rdb introductionKim Phillips2007-04-25-0/+1
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| * | | | | mpc83xx: Add generic PCI setup code.Scott Wood2007-04-23-1/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Board code can now request the generic setup code rather than having to copy-and-paste it for themselves. Boards should be converted to use this once they're tested with it. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | | mpc83xx: Add 831x support to speed.c.Scott Wood2007-04-23-26/+42
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | | mpc83xx: Change PVR_83xx to PVR_E300C1-3, and update checkcpu().Scott Wood2007-04-23-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than misleadingly define PVR_83xx as the specific type of 83xx being built for, the PVR of each core revision is defined. checkcpu() now prints the core that it detects, rather than aborting if it doesn't find what it thinks it wants. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | | mpc83xx: Recognize SPR values for MPC8311 and MPC8313.Scott Wood2007-04-23-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | | Merge git://www.denx.de/git/u-bootKim Phillips2007-04-23-2621/+10523
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| * | | | | | Fix two bugs for MPC83xx DDR2 controller SPD InitXie Xiaobo2007-04-12-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a few bugs in the cpu/mpc83xx/spd_sdram.c the first bug is that the picos_to_clk routine introduces a huge rounding error in 83xx. the second bug is that the mode register write recovery field is tWR-1, not tWR >> 1.
* | | | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-microblazeWolfgang Denk2007-05-16-236/+88
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| * | | | | | | add: reading special purpose registersMichal Simek2007-05-08-2/+2
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| * | | | | | | add: Microblaze V5 exception handlingMichal Simek2007-05-08-2/+8
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| * | | | | | | Merge git://www.denx.de/git/u-bootMichal Simek2007-05-08-2917/+10472
| |\ \ \ \ \ \ \ | | | |_|_|_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: include/asm-microblaze/microblaze_intc.h include/linux/stat.h
| * | | | | | | new: USE_MSR_INTR supportMichal Simek2007-05-07-6/+21
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| * | | | | | | fix: interrupt handlerMichal Simek2007-05-07-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | remove asm code
| * | | | | | | fix: remove asm codeMichal Simek2007-05-07-223/+17
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| * | | | | | | fix: clean interruptMichal Simek2007-05-07-3/+13
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