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* ColdFire: Add M5208EVB and MCF520x CPU supportTsiChung Liew2009-07-14-14/+199
| | | | Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* ColdFire: Update for M54451EVBTsiChung Liew2009-07-14-35/+56
| | | | | | | | Update serial boot DRAM's Internal RAM, vector table and DRAM in start.S, serial flash's read status command over SPI and NOR flash. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* MPC512x: factor out common codeWolfgang Denk2009-07-14-1/+122
| | | | | | | | | | | | | | Now that we have 3 boards for the MPC512x it turns out that they all use the very same fixed_sdram() code. This patch factors out this common code into cpu/mpc512x/fixed_sdram.c and adds a new header file, include/asm-ppc/mpc512x.h, with some macros, inline functions and prototype definitions specific to MPC512x systems. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* Merge branch 'master' of /home/wd/git/u-boot/masterWolfgang Denk2009-07-14-11/+509
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| * Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-07-13-2/+188
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| | * at91: Introduction of at91sam9g10 SOC.Sedji Gaouaou2009-07-12-0/+1
| | | | | | | | | | | | | | | | | | | | | AT91sam9g10 is an ARM 926ej-s SOC. It is an evolution of the at91sam9261 with a faster clock speed: 266/133MHz. Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
| | * at91: Introduction of at91sam9g45 SOC.Sedji Gaouaou2009-07-12-2/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz. It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of peripherals. The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES. On the board you can find 2 USART, USB high speed, a 480*272 LG lcd, ethernet, gpio/joystick/buttons. Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2009-07-13-0/+296
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| | * | sh: unify linker scriptJean-Christophe PLAGNIOL-VILLARD2009-07-08-0/+296
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | all sh boards use the same cpu linker script so move it to cpu/$(CPU) that could be overwrite in following order SOC BOARD via the corresponding config.mk tested on r2dplus Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-07-13-7/+23
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| | * | ppc4xx: Set default PCI device ID for 405EP boardsMatthias Fuchs2009-07-10-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code only sets the PCI vendor id to 0x1014 and leaved device id to 0x0000. Ths patch .... a) uses the correct PCI_VENDOR_ID_IBM macro for this b) sets the default device ID as stated in the UM to 0x0156 by using PCI_DEVICE_ID_IBM_405GP for this. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Move 405EP pci code from cpu_init_f() to __pci_pre_init()Matthias Fuchs2009-07-10-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves some basic PCI initialisation from the 4xx cpu_init_f() to cpu/ppc4xx/4xx_pci.c. The original cpu_init_f() function enabled the 405EP's internal arbiter in all situations. Also the HCE bit in cpc0_pci is always set. The first is not really wanted for PCI adapter designs and the latter is a general bug for PCI adapter U-Boots. Because it enables PCI configuration by the system CPU even when the PCI configuration has not been setup by the 405EP. The one and only correct place is in pci_405gp_init() (see "Set HCE bit" comment). So for compatibility reasons the arbiter is still enabled in any case, but from weak pci_pre_init() so that it can be replaced by board specific code. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | mpc83xx: USB: fix: access of ehci struct elementsVivek Mahajan2009-07-09-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | It fixes the access to the 'ehci' struct elements for mpc83xx which should have been taken care of in 4ef01010aa4799c759d75e67007fdd3a38c88c8a Sorry about that. Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
* | | board support patch for phyCORE-MPC5200B-tinyJon Smirl2009-07-10-0/+3
|/ / | | | | | | | | | | | | | | | | | | Add support for the Phytec phyCORE-MPC5200B-tiny. Code originally from Pengutronix.de. Created CONFIG_SYS_ATA_CS_ON_TIMER01 define for when IDE CS is on Timer 0/1 Signed-off-by: Jon Smirl <jonsmirl@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca>
* | ppc4xx: Make pll_write globalMatthias Fuchs2009-07-08-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes pll_write on PPC405EP boards global and callable from C code. pll_write can be used to dynamically modify the PLB:PCI divider as it is required for 33/66 MHz pci adapters based on the 405EP. board_early_init_f() is a good place to do that (check M66EN signal and call pll_write() when it is required). Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Remove compilation warning "pci_async_enabled defined but not used"Stefan Roese2009-07-08-0/+2
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Implement is_pci_host() for 405 CPUsMatthias Fuchs2009-07-08-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the is_pci_host() function in a similiar way as it is used on 440 targets. The former path with CONFIG_PCI_HOST == PCI_HOST_AUTO does not build on 405EP targets because checking the PCI arbiter is different. So putting the fixed code into a separate function makes the code more readable. Also using is_pci_host() on 405 brings 405 and 440 PCI code a little bit closer. In preparation for an upcoming 405EP based PMC module I made this function weak so that it can be overwritten from board specific code. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fixed PPC4xx debug compilation error in uic.cAlessio Centazzo2009-07-08-1/+1
| | | | | | | | | | | | | | | | | | | | This patch fixes a debug compilation error for PPC4xx platforms, all other architectures are not affected by this change. The 'handler' pointer was undefined. The fix is exercised and has effect only if DEBUG is defined. Signed-off-by: Alessio Centazzo acpatin@yahoo.com Signed-off-by: Stefan Roese <sr@denx.de>
* | 4xx: Fix compilation warnings and MQ registers dump in SPD DDR2 codeFelix Radensky2009-07-08-17/+25
|/ | | | | | | | | | This patch fixes printf format string compilation warnings in several debug statements. It also fixes the dump of DDR controller MQ registers found on some 44x and 46x platforms. The current register dump code uses incorrect DCRs to access these registers. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Coding style cleanup; update CHANGELOGWolfgang Denk2009-07-07-5/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-07-07-277/+1818
|\ | | | | | | | | | | | | Conflicts: drivers/spi/Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
| * arm: Kirkwood: arch specific updated for ehci-Kirkwood driver supportPrafulla Wadaskar2009-07-06-5/+1
| | | | | | | | | | | | This patch abstracts Kirkwood arch specific changes to support ehci-kirkwood driver Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * arm nomadik: use 1000 as HZ value and rewrite timer codeAlessandro Rubini2009-07-06-139/+27
| | | | | | | | | | | | | | | | | | | | | | | | This sets CONFIG_SYS_HZ to 1000 as required, and completely rewrites timer code, which is now both correct and much smaller. Unused functions like udelay_masked() have been removed as no driver uses them, even the ones that are not currently active for this board. mtu.h is copied literally from the kernel sources. Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * arm nomadik: cleanup resetAlessandro Rubini2009-07-06-12/+1
| | | | | | | | | | | | | | | | There is only one public release of the Nomadik chip, so the ifdef in reset code as well as a define in the config file are not needed Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
| * at91: Add CAN init functionDaniel Gorsulowski2009-07-06-0/+30
| | | | | | | | | | | | | | | | | | To enable CAN init, CONFIG_CAN has to be defined in the board config file and at91_can_hw_init() has to be called in the board specific code. CAN is available on AT91SAM9263 and AT91CAP9 SoC. Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
| * S3C24x0: extract interrupts from timerJean-Christophe PLAGNIOL-VILLARD2009-07-06-21/+56
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * arm920t/interrupts: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2009-07-06-6/+6
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * move L2 cache enable/disable function to cache.c in the omap3 SoC directoryKim, Heung Jun2009-07-06-68/+104
| | | | | | | | | | | | Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com> CC: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * arm: Kirkwood: Basic SOCs supportPrafulla Wadaskar2009-07-06-0/+670
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kirkwood family controllers are highly integrated SOCs based on Feroceon-88FR131/Sheeva-88SV131/arm926ejs cpu core. SOC versions supported:- 1) 88F6281-A0 define CONFIG_KW88F6281_A0 2) 88F6192-A0 define CONFIG_KW88F6192_A0 Other supported features:- 1) get_random_hex() fucntion 2) PCI Express port initialization 3) NS16550 driver support Contributors: Yotam Admon <yotam@marvell.com> Michael Blostein <michaelbl@marvell.com Reviewed-by: Ronen Shitrit <rshitrit@marvell.com> Acked-by: Stefan Rose <sr@denx.de> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * s3c64xx: move the reset_cpu functionMinkyu Kang2009-06-26-16/+36
| | | | | | | | | | | | | | | | Because of the reset_cpu is soc specific, should be move to soc And read reset value from SYS_ID register instead of hard code this patch also supports s3c6410 Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * mx27: basic cpu supportIlya Yanok2009-06-21-0/+533
| | | | | | | | | | | | This patch adds generic code to support Freescale's i.MX27 SoCs. Signed-off-by: Ilya Yanok <yanok@emcraft.com>
| * i.MX31: Create a common device file.Magnus Lilja2009-06-21-0/+57
| | | | | | | | Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
| * MX31: Add NAND SPL for i.MX31.Magnus Lilja2009-06-21-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the NAND SPL framework needed to boot i.MX31 boards from NAND. It has been tested on a i.MX31 PDK board with large page NAND. Small page NANDs should work as well, but this has not been tested. Note: The i.MX31 NFC uses a non-standard layout for large page NANDs, whether this is compatible with a particular setup depends on how the NAND device is programmed by the flash programmer (e.g. JTAG debugger). The patch is based on the work by Maxim Artamonov. Signed-off-by: Maxim Artamonov <scn1874@yandex.ru> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
| * ARM1136: Introduce CONFIG_PRELOADER macro.Magnus Lilja2009-06-21-12/+12
| | | | | | | | | | | | | | | | | | Currently CONFIG_ONENAND_IPL is used in a number of #ifdef's in start.S. In preparation for adding support for NAND SPL the macro CONFIG_PRELOADER is introducted and replaces the CONFIG_ONENAND_IPL in start.S. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
| * at91: unify nor boot supportJean-Christophe PLAGNIOL-VILLARD2009-06-21-2/+284
| | | | | | | | | | | | the lowlevel init sequence is the same so unify it Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | 83xx: Add support for fsl_dma driverPeter Tyser2009-07-02-121/+4
| | | | | | | | | | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Reviewed-by: Ira W. Snyder <iws@ovro.caltech.edu> Tested-by: Ira W. Snyder <iws@ovro.caltech.edu> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | 83xx: Replace CONFIG_ECC_INIT_VIA_DDRC referencesPeter Tyser2009-07-02-1/+1
| | | | | | | | | | | | | | | | | | | | Update 83xx architecture's CONFIG_ECC_INIT_VIA_DDRC references to CONFIG_ECC_INIT_VIA_DDRCONTROLLER, which other Freescale architectures use Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl_ddr: Fix DDR3 calculation of rank density with 8GB or moreTimur Tabi2009-07-01-1/+1
| | | | | | | | | | | | | | | | | | | | The calculate for rank density in compute_ranksize() for DDR3 used all integers for the expression, so the result was also a 32-bit integer, even though the 'bsize' variable is a u64. Fix the expression to calculate a true 64-bit value. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl_dma: Break out common memory initialization functionPeter Tyser2009-07-01-25/+1
| | | | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | 8xxx: Move dma_init() call to common codePeter Tyser2009-07-01-3/+6
| | | | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl_dma: Move dma function prototypes to common header filePeter Tyser2009-07-01-4/+0
| | | | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | 8xxx: Rename dma_xfer() to dmacpy()Peter Tyser2009-07-01-32/+30
| | | | | | | | | | | | | | | | Also update dmacpy()'s argument order to match memcpy's and use phys_addr_t/phy_size_t for address/size arguments Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | 8xxx: Break out DMA code to a common filePeter Tyser2009-07-01-102/+0
| | | | | | | | | | | | | | | | DMA support is now enabled via the CONFIG_FSL_DMA define instead of the previous CONFIG_DDR_ECC Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | 86xx: Add CPU_TYPE_ENTRY supportKumar Gala2009-06-30-12/+21
|/ | | | | | | | Unify with 83xx and 85xx and use CPU_TYPE_ENTRY. We are going to use this to convey the # of cores and DDR width in the near future so its good to keep in sync. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Blackfin: bump up default JTAG console timeoutVivi Li2009-06-15-1/+1
| | | | | | | | | | The debug tools that interface with the other side of the JTAG console got much slower when generalizing things, so bump up the default timeout value on the U-Boot side to cope. Hopefully at some point we can improve the debug tools to speed things back up. Signed-off-by: Vivi Li <vivi.li@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Switched davinci_emac Ethernet driver to use newer APIBen Warren2009-06-15-0/+12
| | | | | | | | Added CONFIG_NET_MULTI to all Davinci boards Removed all calls to Davinci network driver from board code Added cpu_eth_init() to cpu/arm926ejs/cpu.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Moved Davinci Ethernet driver to drivers/netBen Warren2009-06-15-656/+1
| | | | | | This driver has been renamed davinci_emac.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* fsl/85xx, 86xx: Sync up DMA codePeter Tyser2009-06-12-10/+12
| | | | | | | | | | | | | | | | | | | | | The following changes were made to sync up the DMA code between the 85xx and 86xx architectures which will make it easier to break out common 8xxx DMA code: 85xx: - Don't set STRANSINT and SPCIORDER fields in SATR register. These bits only have an affect when the SBPATMU bit is set. - Write 0xffffffff instead of 0xfffffff to clear errors in the DMA status register. We may as well clear all 32 bits of the register... 86xx: - Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers - Add clearing of errors in the DMA status register when initializing the controller - Clear the channel start bit in the DMA mode register after a transfer Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: Create common fsl_dma.h for 85xx and 86xx cpusPeter Tyser2009-06-12-26/+32
| | | | | | | | Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to reduce a large amount of code duplication Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* qe: Pass in uec_info struct through uec_initializeHaiying Wang2009-06-12-34/+7
| | | | | | | | | | | The uec driver contains code to hard code configuration information for the uec ethernet controllers. This patch creates an array of uec_info structures, which are then parsed by the corresponding driver instance to determine configuration. It also creates function uec_standard_init() to initialize all UEC interfaces for 83xx and 85xx. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-12-16 05:49:12 +0000