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* ppc/85xx: Fix how we determine the number of CAM entriesKumar Gala2009-11-13-2/+2
| | | | | | | | We were incorrectly use the max CAM size as the number of entries in the array for setting up the addrmap. We should be using the NENTRY field which is the low 12-bits of TLB1CFG. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl-ddr: Fix the chip-select interleaving issueDave Liu2009-11-12-4/+3
| | | | | | | | | | | commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3 introduced one new bug to chip-select interleaving. Single DDR controller also can do the chip-select interleaving if there is dual-rank or qual-rank DIMMs. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-11-11-1/+1
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| * ppc4xx: 44x_spd_ddr2.c: Fix register macro ECCCR -> ECCES (SDRAM_ECCES)Stefan Roese2009-11-09-1/+1
| | | | | | | | | | | | | | This error only appears when DEBUG is enabled in this driver. That's why it went unnoticed till now. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc/85xx: Fix misc L2 cache enabling bugDave Liu2009-10-31-4/+8
|/ | | | | | | We need loop-check the flash clear lock and enable bit for L2 cache. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Coding Style cleanup; update CHANGELOG, prepare -rc1v2009.11-rc1Wolfgang Denk2009-10-28-31/+29
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+4
| | | | | | | | | | | | | | | | | | eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: MP Boot Page Translation updatePeter Tyser2009-10-27-31/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Fix crashes due to generation of SPE instructionLeon Woestenberg2009-10-26-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot crashed on the last instruction: int parse_stream_outer(struct in_str *inp, int flag) { effa4784: 94 21 ff 38 stwu r1,-200(r1) effa4788: 7c 08 02 a6 mflr r0 effa478c: 42 9f 00 05 bcl- 20,4*cr7+so,effa4790 <parse_stream_outer+0xc> effa4790: 7d 80 00 26 mfcr r12 effa4794: 13 c1 b3 21 evstdd r30,176(r1) ...which is a SPE instruction, although -mno-spe was used. tmp/cross/ppce500v2/bin/powerpc-angstrom-linux-gnuspe-gcc --version powerpc-angstrom-linux-gnuspe-gcc (GCC) 4.3.3 Seems to be a known issue (since 2008-04?!) Googled some, turns out this patch/workaround works for me on MPC8536DS. See http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html for more info Signed-off-by: Leon Woestenberg <leon@sidebranch.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Make L2 support more robustDave Liu2009-10-26-1/+4
| | | | | | | According the user manual, we need loop-check the L2 enable bit set. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master-sync' of git://git.denx.de/u-boot-armWolfgang Denk2009-10-24-854/+1651
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| * arm926ejs: 8-byte align stack to avoid LDRD/STRD problemsSimon Kagstrom2009-10-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | U-boot for Marvell Kirkwood boards no longer work after the EABI changes introduced in commit f772acf8a584067033eff1e231fcd1fb3a00d3d9. This turns out to be caused by a stack alignment issue. The armv5te instructions ldrd/strd instructions require 8-byte alignment to work properly (otherwise undefined behavior). Tested on an OpenRD base board, where both printouts and ubifs stuff now works. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
| * TI OMAP3: make gpmc_config as constNishanth Menon2009-10-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | gpmc_config should not be a variant as it is board specific hence make it a const parameter Fixes issues identified by Dirk: - build issue for zoom2 - warnings for all other OMAP3 platforms using nand/onenand etc Signed-off-by: Nishanth Menon <nm@ti.com>
| * OMAP3: fix warnings when NAND/ONENAND is not usedNishanth Menon2009-10-18-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Fix build warnings by putting specific used variables under required #ifdefs for removing: mem.c:227: warning: unused variable 'f_sec' mem.c:226: warning: unused variable 'f_off' mem.c:225: warning: unused variable 'size' mem.c:224: warning: unused variable 'base' mem.c:222: warning: unused variable 'gpmc_config' Signed-off-by: Nishanth Menon <nm@ti.com>
| * TI: OMAP3: Remove SZ_xx referencesSandeep Paulraj2009-10-18-4/+4
| | | | | | | | | | | | | | This patch removes dependency on the sizes.h header file and removes all references to SZ_xx. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * Clean-up of cpu_arm920t and cpu_arm920t_s3c24x0 codekevin.morfitt@fearnside-systems.co.uk2009-10-13-830/+915
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch re-formats the code in cpu/arm920t and cpu/arm920t/23c24x0 in preparation for changes to add support for the Embest SBC2440-II Board. The changes are as follows: - re-indent the code using Lindent - make sure register layouts are defined using a C struct - replace the upper-case typedef'ed C struct names with lower case non-typedef'ed ones - make sure registers are accessed using the proper accessor functions - run checkpatch.pl and fix any error reports It assumes the following patch has been applied first: - [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009 Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no new warnings or errors were found. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boardskevin.morfitt@fearnside-systems.co.uk2009-10-13-16/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sets CONFIG_SYS_HZ to 1000 for all boards that use the s3c2400 and s3c2410 cpu's which fixes various problems such as the timeouts in tftp being too short. Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no new warnings or errors were found. It was originally submitted on 21/06/2009 but didn't get into the 2009.08 release, and Jean-Pierre made one comment on the original patch (see http://lists.denx.de/pipermail/u-boot/2009-July/055470.html). I've made two changes to the original patch: - it's been re-based to the current release - I've re-named get_timer_raw() to get_ticks() in response to Jean-Pierre's comment This affects the sbc2410, smdk2400, smdk2410 and trab boards. I've copied it directly to the maintainers of all except the sbc2410 which doesn't have an entry in MAINTAINERS. Signed-off-by: Kevin Morfitt <kmorfitt@aselaptop-1.localdomain> Tested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * s5pc1xx: support Samsung s5pc1xx SoCMinkyu Kang2009-10-13-0/+703
| | | | | | | | | | | | | | | | This patch adds support for the Samsung s5pc100 and s5pc110 SoCs. The s5pc1xx SoC is an ARM Cortex A8 processor. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-10-24-3/+85
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| * | ppc4xx: Print PCI synchronous clock frequency upon bootupStefan Roese2009-10-23-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | Some 4xx variants (e.g. 440EP(x)/GR(x)) have an internal synchronous PCI clock. Knowledge about the currently configured value might be helpful. So let's print it out upon bootup. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Add function to check and dynamically change PCI sync clockStefan Roese2009-10-23-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPC440EP(x)/PPC440GR(x): In asynchronous PCI mode, the synchronous PCI clock must meet certain requirements. The following equation describes the relationship that must be maintained between the asynchronous PCI clock and synchronous PCI clock. Select an appropriate PCI:PLB ratio to maintain the relationship: AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz This patch now adds a function to check and reconfigure the sync PCI clock to meet this requirement. This is in preparation for some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this function to not violate the PCI clocking rules. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Update flash size in reg property of the NOR flash nodeStefan Roese2009-10-23-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Till now only the ranges in the ebc node are updated with the values currently configured in the PPC4xx EBC controller. With this patch now the NOR flash size is updated in the device tree blob as well. This is done by scanning the compatible nodes "cfi-flash" and "jedec-flash" for the correct chip select number. This size fixup is enabled for all AMCC eval board right now. Other 4xx boards may want to enable it as well, if this problem with multiple NOR FLASH sizes exists. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | cpu/ppc4xx/fdt.c: avoid strcpy() to constant stringWolfgang Denk2009-10-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | strcpy() was iused with the target address being a pointer to a constant string, which potentially is read-only. Use a (writable) array of characters instead. Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2009-10-24-0/+39
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| * | mpc83xx: mpc8313 - handle erratum IPIC1 (TSEC IRQ number swappage)Kim Phillips2009-10-16-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1 h/w (see AN3545). The base device tree in use has rev. 1 ID numbers, so if on Rev. 2 (and higher) h/w, we fix them up here. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Reviewed-by: Roland Lezuo <roland.lezuo@chello.at>
* | | mpc8xxx: improve LAW error messages when setting up DDRPaul Gortmaker2009-10-16-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When setting up the LAWs for the DDR, if there was an error, you got the not-so-helpful error text "ERROR" and nothing else. Not only is it non-informative, but it is also pretty frustrating trying to grep for "ERROR" in the source. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2009-10-15-0/+3
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| * | Blackfin: reset watchdog in udelay()Mike Frysinger2009-10-13-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | All arches apparently should reset the watchdog in their udelay loop as noted on the mailing list recently: > A comment in flash_status_check() suggests that udelay() is > expected to reset the watchdog, but I can't find any architecture > where it does. If this is missing in other architectures, it should be fixed at the root cause, i. e. in udelay() or in the respective support routines. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | arm: Correct build with CONFIG_SYS_HUSH_PARSER setSimon Kagstrom2009-10-13-0/+1
| | | | | | | | | | | | | | FLAG_PARSE_SEMICOLON is not defined without hush.h, so include that. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* | Add support for Eukrea CPU9260/CPU9G20 SBCTom Rix2009-10-13-1/+2
| | | | | | | | | | | | | | | | | | these boards are built around Atmel's AT91SAM9260/9G20 and have up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND and include a 10/100 Ethernet PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* | Add support for Eukrea CPUAT91 SBCTom Rix2009-10-13-2/+252
| | | | | | | | | | | | | | | | | | CPUAT91 is built around Atmel's AT91RM9200 and has up to 16MB of NOR flash, up to 128MB of SDRAM, and includes a Micrel KS8721 PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* | TI DaVinci: DM646x: Initial Support for DM646x SOCSandeep Paulraj2009-10-13-0/+42
| | | | | | | | | | | | | | | | | | DM646x is an SOC from TI which has both an ARM and a DSP. There are multiple variants of the SOC mainly dealing with different core speeds. This patch adds the initial framework for the DM646x SOC. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | OMAP3 Move cache routine to cache.STom Rix2009-10-13-183/+194
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v7_flush_dcache_all, because it depends on omap ROM code is not generic. Rename the function to 'invalidate_dcache' and move it to the omap cpu directory. Collect the other omap cache routines l2_cache_enable and l2_cache_disable with invalide_dcache into cache.S. This means removing the old cache.c file that contained l2_cache_enable and l2_cache_disable. The conversion from cache.c to cache.S was done most through disassembling the uboot binary. The only significant change was to change the comparision for the return of get_cpu_rev from cmp r0, #0 beq earlier_than_label Which was lost information to cmp r0, #CPU_3XX_ES20 blt earlier_than_label The paths through the enable routine were verified by adding an infinite loop and seeing the hang. Then removing the infinite loop and seeing it continue. The disable routine is similar enough that it was not tested with this method. Run tested by cold booting from nand on beagle and zoom1. Compile tested on MAKEALL arm. Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* Merge branch 'reloc'Wolfgang Denk2009-10-09-33/+59
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| * relocation: Do not relocate NULL pointers.Joakim Tjernlund2009-10-08-24/+48
| | | | | | | | | | | | | | | | | | | | NULL is an absolute value and should not be relocated. After this correction code like: void weak_fun(void) __attribute__((weak)); printf("weak_fun:%p\n", weak_fun); will still print null after relocation. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
| * 85xx: Ensure BSS segment isn't linked at address 0Peter Tyser2009-10-08-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When U-Boot is relocated from flash to RAM pointers are modified accordingly. However, pointers initialzed with NULL values should not be modified so that they maintain their intended NULL value. If the BSS segment is linked at address 0 its address will not be updated as necessary during relocation. This is a temporary workaround. The end goal is to add support to U-Boot to dynamically locate the BSS at an arbitrary address at runtime. When the ability to fixup the BSS inteligently is added, this workaround can be removed and the 85xx link script can put the BSS at a fixed address at link time. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Enable full relocation to RAMPeter Tyser2009-10-03-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | The following changes allow U-Boot to fully relocate from flash to RAM: - Remove linker scripts' .fixup sections from the .text section - Add -mrelocatable to PLATFORM_RELFLAGS for all boards - Define CONFIG_RELOC_FIXUP_WORKS for all boards Previously, U-Boot would partially relocate, but statically initialized pointers needed to be manually relocated. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | mpc512x: fix fixed_sdram() init code.Wolfgang Denk2009-10-08-14/+19
| | | | | | | | | | | | | | | | | | | | Commit 054197ba and later fixes used an array to initialize some of the MDDRC parameters; however, the use of an array turned out to be a bad idea as it was not possible to correlate structure entries to array indices in readable and reliable way. Now we use a struct instead, which makes this self-explanatory. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ppc4xx: Rework cmd reginfoNiklaus Giger2009-10-07-0/+374
| | | | | | | | | | | | | | | | | | | | The command "reginfo" got an overhaul for the ppc4xx. It dumps all the relevant HW configuration registers (address, symbolic name, content). This allows to easily detect errors in *.h files and changes in the HW configuration. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc_4xx: Apply new HW register namesNiklaus Giger2009-10-07-41/+41
| | | | | | | | | | | | | | | | Modify all existing *.c files to use the new register names as seen in the AMCC manuals. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add PPC405EX(r) Rev D supportStefan Roese2009-10-07-10/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older 405EX(r) parts. Here a list: 0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec 0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec Since there are only a few older parts in the field, this patch now changes the PVR's above to represent the new Rev D versions. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phong Vo" <pvo@amcc.com>
* | ppc4xx: Fix msg "initialization as root-complex failed" upon PCIe scanStefan Roese2009-10-07-1/+2
| | | | | | | | | | | | | | | | | | | | This message is printed upon PCIe bus scan, not only upon error, but also if no PCIe device is detected at all. Since this is not an error, let's remove this message in this case. We already have the message "link is not up." if there is no PCIe device present. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* | PPC4xx: Denali core: Fix incorrect DDR row bitsMike Nuss2009-10-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPD detection code for the Denali memory controller used on some ppc4xx processors incorrectly encodes DDR0_42. With certain memory configurations, this can cause the bootwrapper to incorrectly calculate the installed memory size, because the number of row bits is wrong. This patch fixes that encoding. Signed-off-by: Mike Nuss <mike@terascala.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Merge PPC4xx DDR and DDR2 ECC handlingStefan Roese2009-10-02-250/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch merges the ECC handling (ECC parity byte writing) into one file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx. This exception is because only those PPC's use the completely different Denali SDRAM controller core. Previously we had two routines to generate/write the ECC parity bytes. With this patch we now only have one core function left. Tested on Kilauea (no ECC) and Katmai (with and without ECC). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Felix Radensky <felix@embedded-sol.com> Cc: Grant Erickson <gerickson@nuovations.com> Cc: Pieter Voorthuijsen <pv@prodrive.nl>
* | ppc4xx: Reorganize DDR2 ECC handlingFelix Radensky2009-10-02-207/+249
|/ | | | | | | | | | Reorganize DDR2 ECC handling to use common code for SPD DIMMs and soldered SDRAM. Also, use common code to display SDRAM info (ECC, CAS latency) for SPD and soldered SDRAM variants. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-09-30-80/+79
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| * ppc4xx: Remove mtsdram0() marcos and use common mtsdram() insteadStefan Roese2009-09-28-14/+13
| | | | | | | | | | | | Additionally some whitespace coding style fixes. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper caseStefan Roese2009-09-28-65/+65
| | | | | | | | | | | | | | | | | | The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Convert PPC4xx UIC defines from lower case to upper caseStefan Roese2009-09-28-14/+14
| | | | | | | | | | | | | | The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese <sr@denx.de>
* | mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfieldsKim Phillips2009-09-26-107/+154
|/ | | | | | | | | | | | | | | | | | | some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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