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* ppc/85xx: Add tracking of TLB CAM usageKumar Gala2010-01-05-0/+65
| | | | | | | | | We need to track which TLB CAM entries are used to allow us to "dynamically" allocate entries later in the code. For example the SPD DDR code today hard codes which TLB entries it uses. We can now make that pick entries that are free. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Remove is_fsl_pci_agentKumar Gala2010-01-05-41/+3
| | | | | | | | All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent that uses the standard PCI programming model to determine host vs agent/end-point. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add support to set DPAA (data path) devices clock frequenciesKumar Gala2010-01-05-0/+36
| | | | | | Set clock-frequency for Frame Manager 0/1 and Patter Match Engine on p4080. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Don't use pci_cfg on FSL_CORENET platformsKumar Gala2010-01-05-0/+3
| | | | | | | The FSL_CORENET platforms use a completely different means to determine which PCIe port is enabled as well as if its a host or agent/end-point. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add support for e500mc cache stashingKumar Gala2010-01-05-1/+43
| | | | | | | | | | | | | | The e500mc core supports the ability to stash into the L1 or L2 cache, however we need to uniquely identify the caches with an id. We use the following equation to set the various stash-ids: 32 + coreID*2 + 0(L1) or 1(L2) The 0 (for L1) or 1 (for L2) matches the CT field used be various cache control instructions. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* USB Consolidate descriptor definitionsTom Rix2009-12-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The header files usb.h and usbdescriptors.h have the same nameed structure definitions for usb_config_descriptor usb_interface_descriptor usb_endpoint_descriptor usb_device_descriptor usb_string_descriptor These are out right duplicates in usb.h usb_device_descriptor usb_string_descriptor This one has extra unused elements usb_endpoint_descriptor unsigned char bRefresh unsigned char bSynchAddress; These in usb.h have extra elements at the end of the usb 2.0 specified descriptor and are used. usb_config_descriptor usb_interface_descriptor The change is to consolidate the definition of the descriptors to usbdescriptors.h. The dublicates in usb.h are removed. The extra element structure will have their name shorted by removing the '_descriptor' suffix. So usb_config_descriptor -> usb_config usb_interface_descriptor -> usb_interface For these, the common descriptor elements are accessed now by an element 'desc'. As an example - if (iface->bInterfaceClass != USB_CLASS_HUB) + if (iface->desc.bInterfaceClass != USB_CLASS_HUB) This has been compile tested on MAKEALL arm, ppc and mips. Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* Merge branch 'next' of ../nextWolfgang Denk2009-12-15-613/+1560
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| * common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOULHeiko Schocher2009-12-08-4/+0
| | | | | | | | | | | | | | | | | | There is more and more usage of printing 64bit values, so enable this feature generally, and delete the CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL defines. Signed-off-by: Heiko Schocher <hs@denx.de>
| * 5xxx, fdt: move fdt_fixup_memory() to cpu.c fileHeiko Schocher2009-12-08-0/+2
| | | | | | | | | | | | | | | | u-boot updates, before starting Linux, the memory node in the DTS. As this is a "standard" feature, move this functionality to the cpu.c file for mpc5xxx and mpc512x processors. Signed-off-by: Heiko Schocher <hs@denx.de>
| * Merge branch 'master' into nextWolfgang Denk2009-12-07-1/+3
| |\ | | | | | | | | | | | | | | | | | | Conflicts: lib_generic/zlib.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * \ Merge branch 'master' into nextWolfgang Denk2009-12-05-0/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/esd/plu405/plu405.c drivers/rtc/ftrtc010.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | Generic udelay() with watchdog supportIngo van Lil2009-12-05-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de>
| * | | i386: Final RelocationGraeme Russ2009-12-05-121/+23
| | | | | | | | | | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
| * | | i386: Remove inline asm symbols from .dynsymGraeme Russ2009-12-05-0/+6
| | | | | | | | | | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
| * | | i386: Rearrange Interupt HandlingGraeme Russ2009-12-05-246/+417
| | | | | | | | | | | | | | | | | | | | | | | | In preperation for full relocation Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
| * | | i386: Fix race condition when using SC520 timersGraeme Russ2009-12-05-5/+6
| | | | | | | | | | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
| * | | avr32/hsdramc: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2009-11-27-4/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj <at> jcrosoft.com> Cc: Haavard Skinnemoen <haavard.skinnemoen <at> atmel.com>
| * | | arm: A320: Add support for Faraday A320 evaluation boardPo-Yu Chuang2009-11-27-0/+313
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for A320 evaluation board from Faraday. This board uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM. FA526 is an ARMv4 processor and uses the ARM920T source in this patch. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
| * | | OMAP3: Fix SDRC initNishanth Menon2009-11-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defaults are for Infineon DDR timings. Since none of the supported boards currently do XIP boot, these seem to be faulty. fix the values as per the calculations(ACTIMA,B), conf the sdrc power with pwdnen and wakeupproc bits Signed-off-by: Nishanth Menon <nm@ti.com>
| * | | OMAP3:SDRC: Cleanup references to SDPNishanth Menon2009-11-27-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Remove SDP referenced unused defines Signed-off-by: Nishanth Menon <nm@ti.com>
| * | | TI DA8xx: Add DA8xx cpu functionsSekhar Nori2009-11-27-10/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provides initial support for TI OMAP-L1x/DA8xx SoC devices. See http://www.ti.com Provides: Low level initialisation. System clock API. Timer control. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
| * | | TI Davinci timer.c: Remove volatiles and memory mapped structuresNick Thompson2009-11-27-13/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove volatiles and memory mapped structure accesses and replace with readl and writel macro usage. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
| * | | Add a unified s3c24x0 header filekevin.morfitt@fearnside-systems.co.uk2009-11-27-47/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a unified s3c24x0 cpu header file that selects the header file for the specific s3c24x0 cpu from the SOC and CPU configs defined in board config file. This removes the current chain of s3c24-type #ifdef's from the s3c24x0 code. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | S3C6400/SMDK6400: fix stack_setup in start.SSeunghyeon Rhee2009-11-27-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix stack_setup to place the stack on the correct address in DRAM accroding to U-Boot standard and remove conditional compilation by CONFIG_MEMORY_UPPER_CODE macro that is not necessry. This macro was introduced and used only by this board for some unclear reason. The definition of this macro is also removed because it's not referenced elsewhere. Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com> Tested-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | s3c64xx: move s3c64xx header files to asm-arm/arch-s3c64xxMinkyu Kang2009-11-27-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the s3c64xx header files from include/ to include/asm-arm/arch-s3c64xx Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Move s3c24x0 header files to asm-arm/arch-s3c24x0/kevin.morfitt@fearnside-systems.co.uk2009-11-27-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the s3c24x0 header files from include/ to include/asm-arm/arch-s3c24x0/. checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due to a non-UTF8 character in David M?ller's name: ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8 #489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3: + * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch As David's name correctly contains a non-UTF8 character I haven't fixed these errors. The 3 warnings were all because of the use of 'volatile' in s3c24x0.h: WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt #673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35: +typedef volatile u8 S3C24X0_REG8; +typedef volatile u16 S3C24X0_REG16; +typedef volatile u32 S3C24X0_REG32; I'll fix these errors in another patch. Tested by running MAKEALL for ARM8 targets and ensuring there were no new errors or warnings. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | ppc4xx: Cleanup PPC4xx I2C infrastructureStefan Roese2009-11-23-102/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up the PPC4xx I2C intrastructure: - Use C struct to describe the I2C registers instead of defines - Coding style cleanup (braces, whitespace, comments, line length) - Extract common code from i2c_read() and i2c_write() - Remove unneeded IIC defines from ppc405.h & ppc440.h Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Remove some testing code from 4xx_pcie.cStefan Roese2009-11-23-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | This code got included accidentally. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Consolidate pci_master_init() functionStefan Roese2009-11-19-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the duplicted implementations of the pci_master_init() function by introducing a weak default function for it. It can be overridden by a board specific version. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Consolidate pci_pre_init() functionStefan Roese2009-11-19-23/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the duplicted implementations of the pci_pre_init() function by introducing a weak default function for it. This weak default has a different implementation for some PPC variants. It can be overridden by a board specific version. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Consolidate pci_target_init() functionStefan Roese2009-11-19-0/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the duplicted implementations of the pci_target_init() function by introducing a weak default function for it. This weak default has a different implementation for 440EP(x)/GR(x) PPC's. It can be overridden by a board specific version (e.g. PMC440, korat). Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
| * | | Merge branch 'master' into nextWolfgang Denk2009-11-15-11/+14
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| * | | | ppc/85xx: make boot from NAND full relocation to RAMMingkai Hu2009-11-13-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Take advantage of the latest full relocation commit of PPC platform for boot from NAND. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
| * | | | ppc4xx: Switch to I2C bus numer 0 for chip_config commandStefan Roese2009-11-10-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All currently available 4xx derivats have the I2C bootstrap EEPROM located on I2C bus number 0. This patch now first sets this bus number, so that the chip_config command also works for board with multiple I2C busses, like Katmai. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Remove duplicated is_pci_host() functionsStefan Roese2009-11-09-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a weak default function for is_pci_host(), returning 1. This is the default behaviour, since most boards only implement PCI host functionality. This weak default can be overridden by a board specific version if needed. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Consolidate 4xx PCIe board specific configurationStefan Roese2009-11-09-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch consolidates the PPC4xx board specific PCIe configuration code. This way the duplicated code is removed. Boards can implement a special, non standard behaviour (e.g. number of PCIe slots, etc) by overriding the weak default functions. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Add common ppc4xx linker scriptStefan Roese2009-11-02-0/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This linker script can be used by all PPC4xx platforms. It works for PPC405 and PPC440 platforms. Boards which need a board specific linker script can override this default linker script in board/*/config.mk. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | mpc83xx: boot time regression, move LCRR setup back to cpu_init_fPeter Korsgaard2009-12-09-32/+29
| |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields) moved the LCRR assignment to after relocation to RAM because of the potential problem with changing the local bus clock while executing from flash. This change unfortunately adversely affects the boot time, as running all code up to cpu_init_r can cause significant slowdown. E.G. on a 8347 board a bootup time increase of ~600ms has been observed: 0.020 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz 0.168 RS: 232 0.172 I2C: ready 0.176 DRAM: 64 MB 1.236 FLASH: 32 MB Versus: 0.016 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz 0.092 RS: 232 0.092 I2C: ready 0.096 DRAM: 64 MB 0.644 FLASH: 32 MB So far no boards have needed the late LCRR setup, so simply revert it for now - If it is needed at a later time, those boards can either do their own final LCRR setup in board code (E.G. in board_early_init_r), or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do the setup in cpu_init_r. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | | help: Correct syntax of nandecc help output.Robert P. J. Day2009-12-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | "nandecc" help output should not reproduce the command name, nor have a trailing newline. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* | | | trab: fix warning: implicit declaration of function 'disable_vfd'Wolfgang Denk2009-12-07-0/+2
| |_|/ |/| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | mpc8260: move FDT memory node fixup into common CPU code.Marcel Ziswiler2009-11-22-0/+1
| |/ |/| | | | | | | Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com> Tested-by: Heiko Schocher <hs@denx.de>
* | ppc/85xx: Fix how we determine the number of CAM entriesKumar Gala2009-11-13-2/+2
| | | | | | | | | | | | | | | | We were incorrectly use the max CAM size as the number of entries in the array for setting up the addrmap. We should be using the NENTRY field which is the low 12-bits of TLB1CFG. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl-ddr: Fix the chip-select interleaving issueDave Liu2009-11-12-4/+3
| | | | | | | | | | | | | | | | | | | | | | commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3 introduced one new bug to chip-select interleaving. Single DDR controller also can do the chip-select interleaving if there is dual-rank or qual-rank DIMMs. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-11-11-1/+1
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| * | ppc4xx: 44x_spd_ddr2.c: Fix register macro ECCCR -> ECCES (SDRAM_ECCES)Stefan Roese2009-11-09-1/+1
| |/ | | | | | | | | | | | | This error only appears when DEBUG is enabled in this driver. That's why it went unnoticed till now. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc/85xx: Fix misc L2 cache enabling bugDave Liu2009-10-31-4/+8
|/ | | | | | | We need loop-check the flash clear lock and enable bit for L2 cache. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Coding Style cleanup; update CHANGELOG, prepare -rc1v2009.11-rc1Wolfgang Denk2009-10-28-31/+29
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+4
| | | | | | | | | | | | | | | | | | eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: MP Boot Page Translation updatePeter Tyser2009-10-27-31/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Fix crashes due to generation of SPE instructionLeon Woestenberg2009-10-26-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot crashed on the last instruction: int parse_stream_outer(struct in_str *inp, int flag) { effa4784: 94 21 ff 38 stwu r1,-200(r1) effa4788: 7c 08 02 a6 mflr r0 effa478c: 42 9f 00 05 bcl- 20,4*cr7+so,effa4790 <parse_stream_outer+0xc> effa4790: 7d 80 00 26 mfcr r12 effa4794: 13 c1 b3 21 evstdd r30,176(r1) ...which is a SPE instruction, although -mno-spe was used. tmp/cross/ppce500v2/bin/powerpc-angstrom-linux-gnuspe-gcc --version powerpc-angstrom-linux-gnuspe-gcc (GCC) 4.3.3 Seems to be a known issue (since 2008-04?!) Googled some, turns out this patch/workaround works for me on MPC8536DS. See http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html for more info Signed-off-by: Leon Woestenberg <leon@sidebranch.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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