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* Fix merge problemsStefan Roese2008-08-06-40/+43
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Minor coding style cleanup of Xilinx Virtex5 ml507 supportStefan Roese2008-07-18-36/+7
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: CPU PPC440x5 on Virtex5 FXRicardo Ribalda Delgado2008-07-18-153/+361
| | | | | | | | | | | -This patchs gives support for the embbedded ppc440 on the Virtex5 FPGAs -interrupts.c divided in uic.c and interrupts.c -xilinx_irq.c for xilinx interrupt controller -Include modifications propossed by Stefan Roese Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of /home/stefan/git/u-boot/u-boot into nextStefan Roese2008-07-17-35/+74
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| * Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-07-15-25/+62
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| | * 85xx: Cleanup L2 cache size detectionKumar Gala2008-07-14-17/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L2 size detection code was a bit confusing and we kept having to add code to it to handle new processors. Change the sense of detection so we look for the older processors that aren't changing. Also added support for 1M cache size on 8572. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * 8xxx-fdt: set ns16550 clock from CFG_NS16550_CLK, not bi_busfreqPaul Gortmaker2008-07-14-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards that have external 16550 UARTs don't have a direct tie between bi_busfreq and the clock used for the UARTs. Boards that do have such a tie should set CFG_NS16550_CLK to be get_bus_freq(0) -- which most of them do already. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
| | * Change the temp map to ROM to align addresses to page size.Andrew Klossner2008-07-14-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With a page size of BOOKE_PAGESZ_16M, both the real and effective addresses must be multiples of 16MB. The hardware silently truncates them so the code happens to work. This patch clarifies the situation by establishing addresses that the hardware doesn't need to truncate. Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * mpc85xx: use IS_E_PROCESSOR macroKim Phillips2008-07-14-1/+1
| | | | | | | | | | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * fdt: add crypto node handling for MPC8{3, 5}xxE processorsKim Phillips2008-07-14-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | Delete the crypto node if not on an E-processor. If on 8360 or 834x family, check rev and up-rev crypto node (to SEC rev. 2.4 property values) if on an 'EA' processor, e.g. MPC8349EA. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | ARM DaVinci: Remove extern phy_t declaration by moving code to proper placeHugo Villeneuve2008-07-14-0/+2
| | | | | | | | | | | | | | | | | | | | | ARM DaVinci: Remove extern phy_t declaration by moving code to proper place. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
| * | Fix some more printf() format problems.Kumar Gala2008-07-14-2/+2
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | cpu/i386/serial.c: Fix syntax errorsWolfgang Denk2008-07-14-2/+2
| | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | Code cleanup: fix old style assignment ambiguities like "=-" etc.Wolfgang Denk2008-07-14-3/+3
| | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | Fix printf() format issues with sizeof_t types by using %zuWolfgang Denk2008-07-14-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | Fix some more printf() format issues.Wolfgang Denk2008-07-13-1/+1
| |/ | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge branch 'master' of /home/stefan/git/u-boot/u-boot into nextStefan Roese2008-07-14-30/+67
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| * Fix some more printf() format issues.Jean-Christophe PLAGNIOL-VILLARD2008-07-13-2/+4
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * Fix build time warnings in function mmc_decode_csd()Marcel Ziswiler2008-07-13-1/+1
| | | | | | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * ARM: Fix for broken compilation when defining CONFIG_CMD_ELFHugo Villeneuve2008-07-13-12/+39
| | | | | | | | | | | | caused by missing dcache status/enable/disable functions. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
| * ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boardsStefan Roese2008-07-13-2/+10
| | | | | | | | | | | | | | | | | | This patch removes some ft_board_setup() functions from some 4xx boards. This can be done since we now have a default weak implementation for this in cpu/ppc4xx/fdt.c. Only board in need for a different/custom implementation like canyonlands need their own version. Signed-off-by: Stefan Roese <sr@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-boot-coldfireWolfgang Denk2008-07-13-13/+21
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| | * ColdFire: Fix FB CS not setup properly for Mcf5282TsiChung Liew2008-07-11-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | Remove all CFG_CSn_RO in cpu/mcf52x2/cpu_init.c. If CFG_CSn_RO is defined as 0, the chipselect will not be assigned. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| | * ColdFire: Fix incorrect define for mcf5227x and mcf5445x RTCTsiChung Liew2008-07-11-2/+2
| | | | | | | | | | | | | | | | | | | | | Rename CONFIG_MCFTMR to CONFIG_MCFRTC to include real time clock module in cpu/<cf arch>/cpu_init.c Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| | * ColdFire: Fix compiling error for MCF5275TsiChung Liew2008-07-11-1/+1
| | | | | | | | | | | | | | | | | | | | | The compiling error was caused by missing a closed parentheses in speed.c Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| | * ColdFire: Change invalid JMP to BRA caught by new v4e toolchainTsiChung Liew2008-07-11-2/+2
| | | | | | | | | | | | Signed-off-by: Kurt Mahan <kmahan@freescale.com>
| | * ColdFire: Add -got=single param for new linux v4e toolchainsTsiChung Liew2008-07-11-0/+12
| | | | | | | | | | | | Signed-off-by: Kurt Mahan <kmahan@freescale.com>
| * | ppc4xx: Fix include sequence in 4xx_pcie.cStefan Roese2008-07-11-3/+3
| |/ | | | | | | | | | | | | | | | | This patch now moves common.h to the top of the inlcude list. This is needed for boards with CONFIG_PHYS_64BIT set (e.g. katmai), so that the phys_size_t/phys_addr_t are defined to the correct size in this driver. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix compile warning in 44x_spd_ddr2.cStefan Roese2008-07-11-2/+2
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Rework 440GX UIC handlingStefan Roese2008-07-11-85/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch reworks the 440GX interrupt handling so that the common 4xx code can be used. The 440GX is an exception to all other 4xx variants by having the cascading interrupt vectors not on UIC0 but on a special UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt handling is simpler without any 440GX special cases. Also some additional cleanup to cpu/ppc4xx/interrupt.c is done. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Consolidate PPC4xx UIC definesStefan Roese2008-07-11-328/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This 2nd patch now removes all UIC mask bit definition. They should be generated from the vectors by using the UIC_MASK() macro from now on. This way only the vectors need to get defined for new PPC's. Also only the really used interrupt vectors are now defined. This makes definitions for new PPC versions easier and less error prone. Another part of this patch is that the 4xx emac driver got a little cleanup, since now the usage of the interrupts is clearer. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Consolidate PPC4xx UIC definesStefan Roese2008-07-11-5/+2
| | | | | | | | | | | | | | | | | | This patch is the first step to consolidate the UIC related defines in the 4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next steps. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boardsStefan Roese2008-07-11-2/+10
| | | | | | | | | | | | | | | | | | This patch removes some ft_board_setup() functions from some 4xx boards. This can be done since we now have a default weak implementation for this in cpu/ppc4xx/fdt.c. Only board in need for a different/custom implementation like canyonlands need their own version. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix merge problems in 44x_spd_ddr2.cStefan Roese2008-07-11-16/+19
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add MII mode support to the EMAC RGMII BridgeGrant Erickson2008-07-11-11/+69
| | | | | | | | | | | | | | | | | | This patch adds support for placing the RGMII bridge on the PPC405EX(r) into MII/GMII mode and allows a board-specific configuration to specify the bridge mode at compile-time. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add Mnemonics for AMCC/IBM DDR2 SDRAM ControllerGrant Erickson2008-07-11-165/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM controller registers (MODT and INITPLR) used by the PowerPC405EX(r). The MMODE and MEMODE registers are unified with their peer values used for the INITPLR MR and EMR registers, respectively. Finally, a spelling typo is correct (MANUEL to MANUAL). With these mnemonics in place, the CFG_SDRAM0_* magic numbers for Kilauea are replaced by equivalent mnemonics to make it easier to compare and contrast other 405EX(r)-based boards (e.g. during board bring-up). Finally, unified the SDRAM controller register dump routine such that it can be used across all processor variants that utilize the IBM DDR2 SDRAM controller core. It produces output of the form: PPC4xx IBM DDR2 Register Dump: ... SDRAM_MB0CF[40] = 0x00006701 ... which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included since it is not uncommon that the DCR values in header files get mixed up and it helps to validate, at a glance, they match what is printed in the user manual. Tested on: AMCC Kilauea/Haleakala: - NFS Linux Boot: PASSED - NAND Linux Boot: PASSED Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add initial 460SX defines for the cpu/ppc4xx directory.Feng Kan2008-07-11-4/+54
|/ | | | | Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Fix some more print() format errors.Wolfgang Denk2008-07-11-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* silence misc printf formatting compiler warningsKim Phillips2008-07-10-4/+4
| | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc512xWolfgang Denk2008-07-10-17/+6
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| * Configuration changes for ADS5121 Rev 3Martha Marx2008-07-10-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ADS5121 Rev 3 board is now the default config config targets are now ads5121_config Rev 3 board with PCI M41T62 on board RTC 512MB DRAM ads5121_rev2_config Rev 2 board with No PCI 256MB DRAM Signed-off-by: Martha Marx <mmarx@silicontkx.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: John Rigby <jrigby@freescale.com>
| * Consolidate ADS5121 IO Pin configurationMartha Marx2008-07-10-15/+0
| | | | | | | | | | | | | | | | | | | | | | Consolidate ADS5121 IO Pin configuration to one file board/ads5121/iopin.c. Remove pin config from cpu/mpc512x/fec.c Signed-off-by: Martha Marx <mmarx@silicontkx.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: John Rigby <jrigby@freescale.com>
* | Merge commit 'wd/master'Jon Loeliger2008-07-10-892/+366
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| * ppc4xx: Fix printf format warnings now visible with the updated format checkStefan Roese2008-07-10-25/+25
| | | | | | | | | | | | | | | | | | This patch fixes ppc4xx related printf format warning. Those warnings are now visible since patch dc4b0b38d4aadf08826f6c31270f1eecd27964fd [Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is really helpful. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Enable support for > 2GB SDRAM on AMCC KatmaiStefan Roese2008-07-10-11/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. To support such configurations, we "only" map the first 2GB via the TLB's. We need some free virtual address space for the remaining peripherals like, SoC devices, FLASH etc. Note that ECC is currently not supported on configurations with more than 2GB SDRAM. This is because we only map the first 2GB on such systems, and therefore the ECC parity byte of the remaining area can't be written. Signed-off-by: Stefan Roese <sr@denx.de>
| * Merge branch 'master' of /home/stefan/git/u-boot/u-bootStefan Roese2008-07-10-801/+130
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| | * Minor coding style cleanup; update CHANGELOGWolfgang Denk2008-07-10-2/+1
| | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * Merge branch 'master' of git://www.denx.de/git/u-boot-nand-flashWolfgang Denk2008-07-10-3/+7
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| | | * NAND: Rename DEBUG to MTDDEBUG to avoid namespace pollution.Scott Wood2008-07-09-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is particularly problematic now that non-NAND-specific code is including <nand.h>, and thus all debugging code is being compiled regardless of whether it was requested, as reported by Scott McNutt <smcnutt@psyent.com>. Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * | Minor spelling fix in comment.Marcel Ziswiler2008-07-10-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
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