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* Fix MPC8260 with ethernet on SCCksi@koi8.net2009-02-09-1/+1
| | | | | | | | This fixes MPC8260 compilation with ethernet on SCC. Probably was a typo or something... Signed-off-by: Sergey Kubushyn <ksi@koi8.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* 82xx serial, smc: Coding-Style cleanup serial SMC driverHeiko Schocher2009-02-10-36/+18
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* 82xx serial, smc: add configurable SMC Rx buffer lenHeiko Schocher2009-02-10-37/+60
| | | | | | | | | | | | | | This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN. With this option it is possible to allow the receive buffer for the SMC on 82xx to be greater then 1. In case CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the old version. When defining CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE must be defined to setup the maximum idle timeout for the SMC. Signed-off-by: Heiko Schocher <hs@denx.de>
* ppc: Move CONFIG_MAX_MEM_MAPPED to common config.hKumar Gala2009-02-10-3/+0
| | | | | | | | Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent between the two current users (lib_ppc/board.c, 44x SPD DDR2). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de>
* mpc86xx: Add support to populate addr map based on BATsBecky Bruce2009-02-10-0/+27
| | | | | | | If CONFIG_ADDR_MAP is enabled, update the address map whenever we write a bat. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarityKumar Gala2009-02-07-13/+13
| | | | | | | | | | The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-coldfireWolfgang Denk2009-02-07-3/+10
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| * Coldfire: M5271: Allow board header file to specify clock multiplierRichard Retanubun2009-02-06-1/+6
| | | | | | | | | | | | | | | | | | M5271 dynamic clock multiplier. It is currently fixed at 100MHz. Allow the board header file to set their own multiplier and divider. Added the #define for the multiplier and divider to the cpu header file. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
| * Coldfire: M5271EVB: Remove usage of CONFIG_SYS_FECI2CRichard Retanubun2009-02-06-1/+2
| | | | | | | | | | | | | | Discontinue the use of CONFIG_SYS_FECI2C (only used by M5271EVB). Use read-modify-write to activate the FEC pins without disabling I2C. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
| * Coldfire: Fix half-baud UART by adding M5271 to Coldfire v2 core listRichard Retanubun2009-02-06-1/+2
| | | | | | | | | | | | | | | | | | Added the CONFIG_M5271 to the list of Coldfire V2 processor. This was causing the bus clock (not CPU clock) to be declared twice as fast as it actually is. This causes UARTS to operate at half the specified baudrate. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2009-02-07-121/+108
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| * | Blackfin: dynamically update UART speed when initializingMike Frysinger2009-02-05-91/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, booting over the UART required the baud rate to be known ahead of time. Using a bit of tricky simple math, we can calculate the new board rate based on the old divisors. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
| * | Blackfin: add support for fast SPI reads with Boot ROMMike Frysinger2009-02-05-8/+17
| | | | | | | | | | | | | | | | | | | | | Newer Blackfin boot roms support using the fast SPI read command rather than just the slow one. If the functionality is available, then use it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: check for reserved settings in DDR MMRsMike Frysinger2009-02-05-0/+7
| | | | | | | | | | | | | | | | | | | | | Some bits of the DDR MMRs should not be set. If they do, bad things may happen (like random failures or hardware destruction). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: set default voltage levels for BF538/BF539 partsMike Frysinger2009-02-05-0/+3
| | | | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: use on-chip syscontrol() rom function when availableMike Frysinger2009-02-05-22/+38
| |/ | | | | | | | | | | | | | | Newer Blackfin's have an on-chip rom with a syscontrol() function that needs to be used to properly program the memory and voltage settings as it will include (possibly critical) factory tested bias values. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-02-07-5/+26
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| * | ppc4xx: Make PCIE support selectableDirk Eibach2009-02-06-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | On some platforms PCIE support is not required, but would be included because the cpu supports it. To reduce fooprint it is now configurable via CONFIG_PCI_DISABLE_PCIE. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Only fixup opb attached UARTsMatthias Fuchs2009-02-06-2/+22
| |/ | | | | | | | | | | | | | | | | This patch updates the fdt UART clock fixup code to only touch CPU internal UARTs on 4xx systems. Only these UARTs are definitely clocked by gd->uart_clk. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxWolfgang Denk2009-02-07-0/+397
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| * ADS5121 Add IC Ident Module (IIM) supportMartha Marx2009-02-03-0/+397
| | | | | | | | | | | | | | | | | | | | | | | | IIM (IC Identification Module) is the fusebox for the mpc5121. Use #define CONFIG_IIM to turn on the clock for this module use #define CONFIG_CMD_FUSE to add fusebox commands. Fusebox commands include the ability to read the status, read the register cache, override the register cache, program the fuses and sense them. Signed-off-by: Martha Marx <mmarx@silicontkx.com> Signed-off-by: John Rigby <jrigby@freescale.com>
* | Blackfin: rewrite cache handling functionsMike Frysinger2009-02-02-46/+72
| | | | | | | | | | | | | | Take the cache flush functions from the kernel as they use hardware loops in order to get optimal performance. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: enable --gc-sectionsMike Frysinger2009-02-02-0/+1
| | | | | | | | | | | | | | Start building all Blackfin boards with -ffunction-sections/-fdata-sections and linking with --gc-sections. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: dont check baud if it wont actually get usedMike Frysinger2009-02-02-1/+5
|/ | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-02-01-0/+3169
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| * Initial support for Nomadik 8815 development boardAlessandro Rubini2009-01-24-0/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | The NMDK8815 board is distributed by ST Microelectornics. Other (proprietary) code must be run to unlock the CPU before U-Boot runs. doc/README.nmdk8815 outlines the boot sequence. This is the initial port, with basic infrastructure and a working serial port. Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stnwireless.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * OMAP3: Add common board, interrupt and system infoDirk Behme2009-01-24-0/+895
| | | | | | | | | | | | Add common board, interrupt and system info code. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
| * OMAP3: Add common clock, memory and low level codeDirk Behme2009-01-24-0/+1098
| | | | | | | | | | | | Add common clock, memory and low level code Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
| * OMAP3: Add common cpu and start codeDirk Behme2009-01-24-0/+922
| | | | | | | | | | | | Add common cpu and start code. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netWolfgang Denk2009-02-01-12/+57
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| * | mgcoge make ether_scc.c work with CONFIG_NET_MULTIGary Jennejohn2009-01-24-12/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is needed for mgcoge because it uses two ethernet drivers. Add a check for the presence of the PIGGY board on mgcoge. Without this board networking cannot work and the initialization must be aborted. Only allocate rtx once to prevent DPRAM exhaustion. Initialize ether_scc.c and the keymile-specific HDLC driver (to be added soon) in eth.c. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | sh: sh_eth: Change new network APINobuhiro Iwamatsu2009-01-24-0/+8
| |/ | | | | | | | | | | | | sh_eth used old network API. This patch changed new API. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | ixp: move serial to drivers/serialJean-Christophe PLAGNIOL-VILLARD2009-01-31-126/+0
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ixp: move pci init in arm/board instead of cpuJean-Christophe PLAGNIOL-VILLARD2009-01-31-3/+0
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ixp: move pci drivers to drivers/pciJean-Christophe PLAGNIOL-VILLARD2009-01-31-572/+0
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ixp: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2009-01-31-10/+10
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ixp: add missing os defineJean-Christophe PLAGNIOL-VILLARD2009-01-31-1/+1
| | | | | | | | | | | | need by arm-elf toolchains and no impact on the arm-linux one Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ixp: remove the option to include the MicrocodeJean-Christophe PLAGNIOL-VILLARD2009-01-31-13/+8
| | | | | | | | | | | | | | instead the board will have to load it from flash or ram which will be specified by npe_ucode env var Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ixp/npe: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2009-01-30-10/+6
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2009-01-28-7/+3
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| * | usb.h: use standard __LITTLE_ENDIAN from Linux headersMike Frysinger2009-01-28-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than forcing people to define a custom "LITTLEENDIAN", just use the __LITTLE_ENDIAN one from the Linux byteorder headers that every arch is already setting up. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Remy Bohmer <linux@bohmer.net>
* | | Blackfin: fixup misc warnings such as printf's and missing castsMike Frysinger2009-01-28-10/+11
| | | | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: allow serial console to be disabledMike Frysinger2009-01-28-0/+8
| | | | | | | | | | | | | | | | | | | | | Some devices have no UART device pulled out, so allow people to disable the driver completely in favor of other methods (like JTAG-console). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: support console-over-JTAGMike Frysinger2009-01-28-4/+130
| | | | | | | | | | | | | | | | | | | | | The Blackfin JTAG has the ability to pass data via a back-channel without halting the processor. Utilize that channel to emulate a console. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: handle new anomalies with resetMike Frysinger2009-01-28-5/+15
| | | | | | | | | | | | | | | | | | Workaround fun new anomalies related to software reset of the processor. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: pass RETX to LinuxMike Frysinger2009-01-28-0/+6
| | | | | | | | | | | | | | | | | | | | | Make sure we save the value of RETX at power on and then pass it on to the kernel so that it can nicely debug a "double-fault-caused-a-reset" crash. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: clarify relocation comment during initMike Frysinger2009-01-28-3/+7
| | | | | | | | | | | | | | | | | | | | | People often ask questions about the init process and when things go from flash to relocated base, so clarify the comments a bit. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: just set SP register directly during initMike Frysinger2009-01-28-3/+2
| | | | | | | | | | | | | | | | | | | | | No need to set the SP register indirectly to the configured value when it can be set directly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: add portmuxing for UARTs on the BF51xMike Frysinger2009-01-28-1/+10
| | | | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: respect CONFIG_CLKIN_HALFMike Frysinger2009-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | As pointed out by Ivan Koryakovskiy, the initialization code was not actually respecting the CONFIG_CLKIN_HALF option when configuring the PLL_CTL register. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
generated by cgit v1.1 at 2024-12-26 16:55:33 +0000