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* ppc4xx: IBM Memory Controller DDR autocalibration routinesAdam Graham2008-09-05-0/+1212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alternate SDRAM DDR autocalibration routine that can be generically used for any PPC4xx chips that have the IBM SDRAM Controller core allowing for support of more DIMM/memory chip vendors and gets the DDR autocalibration values which give the best read latency performance (SDRAM0_RDCC.[RDSS]). Two alternate SDRAM DDR autocalibration algoritm are provided in this patch, "Method_A" and "Method_B". DDR autocalibration Method_A scans the full range of possible PPC4xx SDRAM Controller DDR autocalibration values and takes a lot longer to run than Method_B. Method_B executes in the same amount of time as the currently existing DDR autocalibration routine, i.e. 1 second or so. Normally Method_B is used and it is set as the default method. The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM Controller registers.[bit-field]: 1) SDRAM0_RQDC.[RQFD] 2) SDRAM0_RFDC.[RFFD] This alternate PPC4xx DDR autocalibration code calibrates the following IBM SDRAM Controller registers.[bit-field]: 1) SDRAM0_WRDTR.[WDTR] 2) SDRAM0_CLKTR.[CKTR] 3) SDRAM0_RQDC.[RQFD] 4) SDRAM0_RFDC.[RFFD] and will also use the calibrated settings of the above four registers that produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS] register.[bit-field]. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2008-09-03-28/+183
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| * mpc83xx: clean up cache operations and unlock_ram_in_cache() functionsNick Spence2008-09-03-21/+30
| | | | | | | | | | | | | | | | | | Cleans up some latent issues with the data cache control so that dcache_enable() and dcache_disable() will work reliably (after unlock_ram_in_cache() has been called) Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * mpc83xx: Store and display Arbiter Event Register valuesNick Spence2008-09-03-1/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * mpc83xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cacheNick Spence2008-09-03-4/+5
| | | | | | | | | | | | | | | | | | | | | | This is needed in unlock_ram_in_cache() because it is called from C and will corrupt the small data area anchor that is kept in R2. lock_ram_in_cache() is modified similarly as good coding practice, but is not called from C. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * MPC83XX: Fix GPIO configuration - set gpio level before directionNick Spence2008-09-03-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set DAT value before DIR values to avoid creating glitches on the GPIO signals. Set gpio level register before direction register to inhibit glitches on high level output pins. Dir and data gets cleared at powerup, so high level output lines see a short low pulse between setting the direction and level registers. Issue was seen on a new board with the nReset line of the NOR flash connected to a GPIO. Setting the direction register puts the NOR flash in reset so the next instruction to set the level cannot get executed. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Moved initialization of MPC5xxx_FEC Ethernet driver to CPU directoryBen Warren2008-09-02-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified board_eth_init() functions of boards that have this FEC in addition to other Ethernet controllers. Affected boards: bc3450 icecube mvbc_p o2dnt pm520 total5200 tq5200 Removed initialization of controller from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Moved initialization of MPC512x_FEC Ethernet driver to CPU directoryBen Warren2008-09-02-0/+13
| | | | | | | | | | | | | | Added a cpu_eth_init() function to MPC512x CPU directory and removed code from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Moved initialization of Ethernet controllers on Atmel AT91 to board_eth_init()Ben Warren2008-09-02-36/+0
| | | | | | | | | | | | Removed at91sam9_eth_initialize() from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Introduce netdev.h header file and remove externsBen Warren2008-09-02-14/+7
| | | | | | | | | | | | | | This addresses all drivers whose initializers have already been moved to board_eth_init()/cpu_eth_init(). Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Pass in tsec_info struct through tsec_initializeAndy Fleming2008-09-02-55/+24
|/ | | | | | | | | | | | | The tsec driver contains a hard-coded array of configuration information for the tsec ethernet controllers. We create a default function that works for most tsecs, and allow that to be overridden by board code. It creates an array of tsec_info structures, which are then parsed by the corresponding driver instance to determine configuration. Also, add regs, miiregs, and devname fields to the tsec_info structure, so that we don't need the kludgy "index" parameter. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2008-09-01-79/+1410
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| * USB: Add support for OHCI controller on S3C6400Guennadi Liakhovetski2008-08-31-0/+46
| | | | | | | | | | | | | | | | Notice: USB on S3C6400 currently works _only_ with switched off MMU. One could try to enable the MMU, but map addresses 1-to-1, and disable data cache, then it should work too and we could still profit from instruction cache. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
| * ARM: Add arm1176 core with S3C6400 SoCGuennadi Liakhovetski2008-08-31-0/+1285
| | | | | | | | | | | | Based on the original S3C64XX port by Samsung for U-Boot 1.1.6. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
| * ARM DaVinci: Changing function names for EMAC driverSandeep Paulraj2008-08-31-79/+79
| | | | | | | | | | | | | | | | | | | | DM644x is just one of a series of DaVinci chips that use the EMAC driver. By replacing all the function names that start with dm644x_* to davinci_* we make these function more portable. I have tested this change on my EVM. DM6467 is another DaVinci SOC which uses the EMAC driver and i will be sending patches that add DaVinci DM6467 support to the list soon. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-09-01-20/+71
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| * | ppc4xx/NAND: Add select_chip function to 4xx NDFC driverStefan Roese2008-08-30-0/+8
| | | | | | | | | | | | | | | | | | | | | This function is needed for the new NAND infrastructure. We only need a dummy implementation though for the NDFC. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: NAND configurationWolfgang Ocker2008-08-29-1/+5
| | | | | | | | | | | | | | | | | | | | | Made NAND bank configuration setting a config variable. Signed-off-by: Wolfgang Ocker <weo@reccoware.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: fix UIC external_interrupt hang on UIC0Victor Gallardo2008-08-29-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a UIC external_interrupt hang if critical or non-critical interrupt is set at the same time as a normal interrupt is set on UIC0. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Optimizations/Cleanups for IBM DDR2 Memory ControllerProdyut Hazarika2008-08-29-17/+56
| |/ | | | | | | | | | | | | | | | | Removed Magic numbers from Initialization preload registers Tested with Kilauea, Glacier, Canyonlands and Katmai boards About 5-7% improvement seen for LMBench memtests Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2008-09-01-0/+546
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| * | sh: Add support SH2/SH2A which is CPU of Renesas TechnologyNobuhiro Iwamatsu2008-08-31-0/+546
| |/ | | | | | | | | | | | | Add support SH2/SH2A basic function. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxWolfgang Denk2008-08-31-2469/+2
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| * | Move MPC512x_FEC driver to drivers/netBen Warren2008-08-29-1022/+1
| | | | | | | | | | | | Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | Move MPC5xxx_FEC driver to drivers/netBen Warren2008-08-29-1447/+1
| |/ | | | | | | Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | ColdFire: I2C fix for multiple platformsTsiChung Liew2008-08-28-3/+43
|/ | | | Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2008-08-28-2/+4
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| * Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxWolfgang Denk2008-08-28-2/+4
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| | * mpc52xx: added support for the MPC5200 based MUC.MC52 board from MAN.Heiko Schocher2008-08-27-2/+4
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* | | FSL DDR: Remove duplicate setting of cs0_bnds register on 86xx.Kumar Gala2008-08-28-1/+0
|/ / | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-08-28-1260/+589
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| * | mpc85xx: remove redudant code with lib_ppc/interrupts.cKumar Gala2008-08-27-97/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason we duplicated the majority of code in lib_ppc/interrupts.c not show how that happened, but there is no good reason for it. Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why they exist. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc85xx: Add support for the MPC8536Kumar Gala2008-08-27-1/+199
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | mpc85xx: Add support for the MPC8572DS reference boardKumar Gala2008-08-27-2/+2
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | FSL DDR: Remove old SPD support from cpu/mpc85xxKumar Gala2008-08-27-1166/+0
| | | | | | | | | | | | | | | | | | | | | All 85xx boards have been converted to the new code so we can remove the old SPD DDR setup code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | FSL DDR: Add 85xx specific register settingKumar Gala2008-08-27-0/+318
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | FSL DDR: Add e500 TLB helper for DDR codeKumar Gala2008-08-27-0/+64
| |/ | | | | | | | | | | | | Provide a helper function that board code can call to map TLBs when setting up DDR. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Moved initialization of GRETH Ethernet driver to CPU directoryBen Warren2008-08-26-0/+17
| | | | | | | | | | | | | | Added a cpu_eth_init() function to leon2/leon3 CPU directories and removed code from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Moved initialization of MCFFEC Ethernet driver to CPU directoryBen Warren2008-08-26-2/+71
| | | | | | | | | | | | | | Added a cpu_eth_init() function to coldfire CPU directories and removed code from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Moved initialization of FSL_MCDMAFEC Ethernet driver to CPU directoryBen Warren2008-08-26-0/+9
|/ | | | | | | Added a cpu_eth_init() function to cpu/mcf547x_8x directory and removed code from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* FSL DDR: Remove old SPD support from cpu/mpc86xxKumar Gala2008-08-27-1352/+0
| | | | | | | All 86xx boards have been converted to the new code so we can remove the old SPD DDR setup code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add 86xx specific register settingKumar Gala2008-08-27-0/+92
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add DDR2 DIMM paramter supportKumar Gala2008-08-27-0/+339
| | | | | | | | Compute DIMM parameters based upon the SPD information. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add DDR1 DIMM paramter supportKumar Gala2008-08-27-0/+343
| | | | | | | | Compute DIMM parameters based upon the SPD information in spd. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-27-2/+2432
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: add PCISLAVE support to 83XX_GENERIC_PCI setup codeIra W. Snyder2008-08-25-0/+26
| | | | | | | | | This adds a helper function to unlock the PCI configuration bit, so that any extra PCI setup (such as outbound windows, etc.) can be done after using the 83XX_GENERIC_PCI code to set up the PCI bus. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Minor coding style cleanup, updte CHANGELOGWolfgang Denk2008-08-25-7/+7
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* MX31: fix bit masks in function mx31_decode_pll()Jens Gehrlein2008-08-25-2/+2
| | | | | | Bits MPCTL[MFN] and MPCTL[MFD] were not fully covered. Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
* Correct ARM Versatile Timer InitializationGururaja Hebbar K R2008-08-25-4/+35
| | | | | | | | | | | | | | | - According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271), -- Timer Value Register @ TIMER Base + 4 is Read-only. -- Prescale Value (Bits 3-2 of TIMER Control register) can only be one of 00,01,10. 11 is undefined. -- CFG_HZ for Versatile board is set to #define CFG_HZ (1000000 / 256) So Prescale bits is set to indicate - 8 Stages of Prescale, Clock divided by 256 - The Timer Control Register has one Undefined/Shouldn't Use Bit So we should do read/modify/write Operation Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
* ARM DaVinci: Removed redundant NAND initialization code.Hugo Villeneuve2008-08-25-2/+1
| | | | | | ARM DaVinci: Removed redundant NAND initialization code. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
generated by cgit v1.1 at 2024-11-25 03:32:47 +0000