summaryrefslogtreecommitdiff
path: root/cpu
Commit message (Collapse)AuthorAgeLines
* ppc4xx: Print PCI synchronous clock frequency upon bootupStefan Roese2009-10-23-1/+8
| | | | | | | | Some 4xx variants (e.g. 440EP(x)/GR(x)) have an internal synchronous PCI clock. Knowledge about the currently configured value might be helpful. So let's print it out upon bootup. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add function to check and dynamically change PCI sync clockStefan Roese2009-10-23-0/+69
| | | | | | | | | | | | | | | | | | PPC440EP(x)/PPC440GR(x): In asynchronous PCI mode, the synchronous PCI clock must meet certain requirements. The following equation describes the relationship that must be maintained between the asynchronous PCI clock and synchronous PCI clock. Select an appropriate PCI:PLB ratio to maintain the relationship: AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz This patch now adds a function to check and reconfigure the sync PCI clock to meet this requirement. This is in preparation for some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this function to not violate the PCI clocking rules. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update flash size in reg property of the NOR flash nodeStefan Roese2009-10-23-1/+7
| | | | | | | | | | | | | | | Till now only the ranges in the ebc node are updated with the values currently configured in the PPC4xx EBC controller. With this patch now the NOR flash size is updated in the device tree blob as well. This is done by scanning the compatible nodes "cfi-flash" and "jedec-flash" for the correct chip select number. This size fixup is enabled for all AMCC eval board right now. Other 4xx boards may want to enable it as well, if this problem with multiple NOR FLASH sizes exists. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* cpu/ppc4xx/fdt.c: avoid strcpy() to constant stringWolfgang Denk2009-10-23-1/+1
| | | | | | | | | strcpy() was iused with the target address being a pointer to a constant string, which potentially is read-only. Use a (writable) array of characters instead. Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* mpc8xxx: improve LAW error messages when setting up DDRPaul Gortmaker2009-10-16-4/+5
| | | | | | | | | | When setting up the LAWs for the DDR, if there was an error, you got the not-so-helpful error text "ERROR" and nothing else. Not only is it non-informative, but it is also pretty frustrating trying to grep for "ERROR" in the source. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2009-10-15-0/+3
|\
| * Blackfin: reset watchdog in udelay()Mike Frysinger2009-10-13-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All arches apparently should reset the watchdog in their udelay loop as noted on the mailing list recently: > A comment in flash_status_check() suggests that udelay() is > expected to reset the watchdog, but I can't find any architecture > where it does. If this is missing in other architectures, it should be fixed at the root cause, i. e. in udelay() or in the respective support routines. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | arm: Correct build with CONFIG_SYS_HUSH_PARSER setSimon Kagstrom2009-10-13-0/+1
| | | | | | | | | | | | | | FLAG_PARSE_SEMICOLON is not defined without hush.h, so include that. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* | Add support for Eukrea CPU9260/CPU9G20 SBCTom Rix2009-10-13-1/+2
| | | | | | | | | | | | | | | | | | these boards are built around Atmel's AT91SAM9260/9G20 and have up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND and include a 10/100 Ethernet PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* | Add support for Eukrea CPUAT91 SBCTom Rix2009-10-13-2/+252
| | | | | | | | | | | | | | | | | | CPUAT91 is built around Atmel's AT91RM9200 and has up to 16MB of NOR flash, up to 128MB of SDRAM, and includes a Micrel KS8721 PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* | TI DaVinci: DM646x: Initial Support for DM646x SOCSandeep Paulraj2009-10-13-0/+42
| | | | | | | | | | | | | | | | | | DM646x is an SOC from TI which has both an ARM and a DSP. There are multiple variants of the SOC mainly dealing with different core speeds. This patch adds the initial framework for the DM646x SOC. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | OMAP3 Move cache routine to cache.STom Rix2009-10-13-183/+194
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v7_flush_dcache_all, because it depends on omap ROM code is not generic. Rename the function to 'invalidate_dcache' and move it to the omap cpu directory. Collect the other omap cache routines l2_cache_enable and l2_cache_disable with invalide_dcache into cache.S. This means removing the old cache.c file that contained l2_cache_enable and l2_cache_disable. The conversion from cache.c to cache.S was done most through disassembling the uboot binary. The only significant change was to change the comparision for the return of get_cpu_rev from cmp r0, #0 beq earlier_than_label Which was lost information to cmp r0, #CPU_3XX_ES20 blt earlier_than_label The paths through the enable routine were verified by adding an infinite loop and seeing the hang. Then removing the infinite loop and seeing it continue. The disable routine is similar enough that it was not tested with this method. Run tested by cold booting from nand on beagle and zoom1. Compile tested on MAKEALL arm. Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* Merge branch 'reloc'Wolfgang Denk2009-10-09-33/+59
|\
| * relocation: Do not relocate NULL pointers.Joakim Tjernlund2009-10-08-24/+48
| | | | | | | | | | | | | | | | | | | | NULL is an absolute value and should not be relocated. After this correction code like: void weak_fun(void) __attribute__((weak)); printf("weak_fun:%p\n", weak_fun); will still print null after relocation. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
| * 85xx: Ensure BSS segment isn't linked at address 0Peter Tyser2009-10-08-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When U-Boot is relocated from flash to RAM pointers are modified accordingly. However, pointers initialzed with NULL values should not be modified so that they maintain their intended NULL value. If the BSS segment is linked at address 0 its address will not be updated as necessary during relocation. This is a temporary workaround. The end goal is to add support to U-Boot to dynamically locate the BSS at an arbitrary address at runtime. When the ability to fixup the BSS inteligently is added, this workaround can be removed and the 85xx link script can put the BSS at a fixed address at link time. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Enable full relocation to RAMPeter Tyser2009-10-03-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | The following changes allow U-Boot to fully relocate from flash to RAM: - Remove linker scripts' .fixup sections from the .text section - Add -mrelocatable to PLATFORM_RELFLAGS for all boards - Define CONFIG_RELOC_FIXUP_WORKS for all boards Previously, U-Boot would partially relocate, but statically initialized pointers needed to be manually relocated. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | mpc512x: fix fixed_sdram() init code.Wolfgang Denk2009-10-08-14/+19
| | | | | | | | | | | | | | | | | | | | Commit 054197ba and later fixes used an array to initialize some of the MDDRC parameters; however, the use of an array turned out to be a bad idea as it was not possible to correlate structure entries to array indices in readable and reliable way. Now we use a struct instead, which makes this self-explanatory. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ppc4xx: Rework cmd reginfoNiklaus Giger2009-10-07-0/+374
| | | | | | | | | | | | | | | | | | | | The command "reginfo" got an overhaul for the ppc4xx. It dumps all the relevant HW configuration registers (address, symbolic name, content). This allows to easily detect errors in *.h files and changes in the HW configuration. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc_4xx: Apply new HW register namesNiklaus Giger2009-10-07-41/+41
| | | | | | | | | | | | | | | | Modify all existing *.c files to use the new register names as seen in the AMCC manuals. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add PPC405EX(r) Rev D supportStefan Roese2009-10-07-10/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older 405EX(r) parts. Here a list: 0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec 0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec Since there are only a few older parts in the field, this patch now changes the PVR's above to represent the new Rev D versions. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phong Vo" <pvo@amcc.com>
* | ppc4xx: Fix msg "initialization as root-complex failed" upon PCIe scanStefan Roese2009-10-07-1/+2
| | | | | | | | | | | | | | | | | | | | This message is printed upon PCIe bus scan, not only upon error, but also if no PCIe device is detected at all. Since this is not an error, let's remove this message in this case. We already have the message "link is not up." if there is no PCIe device present. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* | PPC4xx: Denali core: Fix incorrect DDR row bitsMike Nuss2009-10-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPD detection code for the Denali memory controller used on some ppc4xx processors incorrectly encodes DDR0_42. With certain memory configurations, this can cause the bootwrapper to incorrectly calculate the installed memory size, because the number of row bits is wrong. This patch fixes that encoding. Signed-off-by: Mike Nuss <mike@terascala.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Merge PPC4xx DDR and DDR2 ECC handlingStefan Roese2009-10-02-250/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch merges the ECC handling (ECC parity byte writing) into one file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx. This exception is because only those PPC's use the completely different Denali SDRAM controller core. Previously we had two routines to generate/write the ECC parity bytes. With this patch we now only have one core function left. Tested on Kilauea (no ECC) and Katmai (with and without ECC). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Felix Radensky <felix@embedded-sol.com> Cc: Grant Erickson <gerickson@nuovations.com> Cc: Pieter Voorthuijsen <pv@prodrive.nl>
* | ppc4xx: Reorganize DDR2 ECC handlingFelix Radensky2009-10-02-207/+249
|/ | | | | | | | | | Reorganize DDR2 ECC handling to use common code for SPD DIMMs and soldered SDRAM. Also, use common code to display SDRAM info (ECC, CAS latency) for SPD and soldered SDRAM variants. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-09-30-80/+79
|\
| * ppc4xx: Remove mtsdram0() marcos and use common mtsdram() insteadStefan Roese2009-09-28-14/+13
| | | | | | | | | | | | Additionally some whitespace coding style fixes. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper caseStefan Roese2009-09-28-65/+65
| | | | | | | | | | | | | | | | | | The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Convert PPC4xx UIC defines from lower case to upper caseStefan Roese2009-09-28-14/+14
| | | | | | | | | | | | | | The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese <sr@denx.de>
* | mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfieldsKim Phillips2009-09-26-107/+154
|/ | | | | | | | | | | | | | | | | | | some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mucmc52, uc101: delete ata@3a00 node, if no CF card is detectedHeiko Schocher2009-09-25-0/+20
| | | | | | | | | | | U-Boot can detect if an IDE device is present or not. If not, and this new config option is activated, U-Boot removes the ATA node from the DTS before booting Linux, so the Linux IDE driver does not probe the device and crash. This is needed for buggy hardware (uc101) where no pull down resistor is connected to the signal IDE5V_DD7. Signed-off-by: Heiko Schocher <hs@denx.de>
* mpc512x: Streamlined fixed_sdram() init sequence.Martha M Stan2009-09-25-35/+69
| | | | | | | | | | | | | | | | | | | Signed-off-by: Martha M Stan <mmarx@silicontkx.com> Minor cleanup: Re-ordered default_mddrc_config[] to have matching indices. This allows to use the same index "N" for source and target fields; before, we had code like this out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]); which always looked like a copy & paste error because 2 != 3. Also, use NULL when meaning a null pointer. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc/p4080: Determine various chip frequencies on CoreNet platformsKumar Gala2009-09-24-4/+127
| | | | | | | | | | The means to determine the core, bus, and DDR frequencies are completely new on CoreNet style platforms. Additionally on p4080 we can have different frequencies for FMAN and PME IP blocks. We need to keep track of the FMAN & PME frequencies since they are used for time stamping capabilities inside each block. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: Handle timebase enabling and frequency reportingKumar Gala2009-09-24-1/+22
| | | | | | | | | On CoreNet style platforms the timebase frequency is the bus frequency defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms the core not longer controls the enabling of the timebase. We now need to enable the boot core's timebase via CCSR register writes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala2009-09-24-0/+5
| | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: CoreNet platfrom style secondary core releaseKumar Gala2009-09-24-3/+65
| | | | | | | | | The CoreNet platform style of bringing secondary cores out of reset is a bit different that the PQ3 style. Mostly the registers that we use to setup boot translation, enable time bases, and boot release the cores have moved around. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: CoreNet platfrom style CCSRBAR settingKumar Gala2009-09-24-18/+54
| | | | | | | | On CoreNet based platforms the CCSRBAR address is split between an high & low register and we no longer shift the address. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
* ppc/85xx: Fix enabling of L2 cacheKumar Gala2009-09-24-3/+4
| | | | | | | We need to flash invalidate the locks in addition to the cache before we enable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQVivek Mahajan2009-09-24-3/+10
| | | | | | | | The code assumed names where just numbers and always prefixed 'mpc'. However newer QorIQ don't follow the mpc naming scheme. Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: add cpu init config file for boot from NANDMingkai Hu2009-09-24-0/+63
| | | | | | | | | When boot from NAND, the NAND flash must be connected to br/or0. Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to it. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: add ld script file for boot from NANDMingkai Hu2009-09-24-0/+67
| | | | | | | | | The first stage 4K image uses a seperate ld script file to generate 4K image. This patch moves it to the cpu/mpc85xx/* to make it avaliable for 85xx platform. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc4xx: Fix PCIE PLL lock on 440SPe Yucca boardRupjyoti Sarmah2009-09-23-8/+15
| | | | | | | | | | u-boot reports a PCIE PLL lock error at boot time on Yucca board, and left PCIe nonfunctional. This is fixed by making u-boot function ppc4xx_init_pcie() to wait 300 uS after negating reset before the first check of the PLL lock. Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate get_OPB_freq()Stefan Roese2009-09-17-75/+15
| | | | | | | | | | | | | All 4xx variants had their own, mostly identical get_OPB_freq() function. Some variants even only had the OPB frequency calculated in this routine and not supplied the sys_info.freqOPB variable correctly (e.g. 405EZ). This resulted in incorrect OPB values passed via the FDT to Linux. This patch now removes all those copies and only uses one function for all 4xx variants (except for IOP480 which doesn't have an OPB). Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix 405EZ uart base baud calculationStefan Roese2009-09-17-1/+5
| | | | | | | With this fix, Linux correctly configures the baudrate when booting with FDT passed from U-Boot to Linux. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc/85xx: Disable all async interrupt sources when we bootKumar Gala2009-09-15-0/+11
| | | | | | | | We should make sure to clear MSR[ME, CE, DE] when we boot an OS image since we have changed the exception vectors and the OSes vectors might not be setup we should avoid async interrupts at all costs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Split out cpu_init_early into its own file for NAND_SPLKumar Gala2009-09-15-51/+77
| | | | | | | By pulling out cpu_init_early we can build just it and not all of cpu_init for NAND_SPL. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Change cpu_init_early_f so we can use with NAND SPLKumar Gala2009-09-15-9/+25
| | | | | | | Use write_tlb and don't use memset so we can use the same code for cpu_init_early_f between NAND SPL and not. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: add boot from NAND/eSDHC/eSPI supportMingkai Hu2009-09-15-1/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch implements these three bootup methods in a unified way - all of these use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM which lets us use the SPD to initialize the SDRAM. For all three bootup methods, the bootup process can be divided into two stages: the first stage will initialize the corresponding controller, configure the L2SRAM, then copy the second stage image to L2SRAM and jump to it. The second stage image is just like the general U-Boot image to configure all the hardware and boot up to U-Boot command line. When boot from NAND, the eLBC controller will first load the first stage image to internal 4K RAM buffer because it's also stored on the NAND flash. The first stage image, also call 4K NAND loader, will initialize the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K NAND loader's code comes from the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. When boot from eSDHC/eSPI, there's no such a first stage image because the CPU ROM code does the same work. It will initialize the L2SRAM according to the config addr/word pairs on the fixed address and initialize the eSDHC/eSPI controller, then load the second stage image to L2SRAM and jump to it. The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the second stage image for all different bootup methods. It's set in the board config file when one of the bootup methods above is selected. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Move code around to prep for NAND_SPLKumar Gala2009-09-15-23/+23
| | | | | | | | If we move some of the functions in tlb.c around we need less ifdefs. The first stage loader just needs invalidate_tlb and init_tlbs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Repack tlb_table to save spaceKumar Gala2009-09-15-4/+5
| | | | | | | | We can pack the initial tlb_table in MAS register format and use write_tlb to set things up. This savings can be helpful for NAND style first stage boot loaders. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Introduce low level write_tlb functionKumar Gala2009-09-15-14/+26
| | | | | | | | | Factor out the code we use to actually write a tlb entry. set_tlb is a logical view of the TLB while write_tlb is a low level matching the MAS registers. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-11-23 05:03:31 +0000