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* 85xx: Add PORDEVSR_PCI1 definePeter Tyser2008-12-04-1/+1
| | | | | | | | | Add define used to determine if PCI1 interface is in PCI or PCIX mode. Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fsl ddr skip interleaving if not supported.Ed Swarthout2008-12-03-12/+17
| | | | | | | | | Removed while(1) hang if memctl_intlv_ctl is set wrong. Remove embedded tabs from strings. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Add CPU 2 errata workaround to all 8548 boardsPeter Tyser2008-12-03-0/+13
| | | | | | | | | | | All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-11-25-26/+44
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| * ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initializationDave Mitchell2008-11-21-7/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expanded OCM TLB to allow access to 64K OCM as well as 256K of internal SRAM. Adjusted internal SRAM initialization to match updated user manual recommendation. OCM & ISRAM are now mapped as follows: physical virtual size ISRAM 0x4_0000_0000 0xE300_0000 256k OCM 0x4_0004_0000 0xE304_0000 64k A single TLB was used for this mapping. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRsDave Mitchell2008-11-21-20/+21
| | | | | | | | | | | | | | | | | | | | | | Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and L2 cache DCRs from ppc440.h to this new header. Also converted these DCR defines from lowercase to uppercase and modified referencing modules to use them. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Clear all potentially pending exceptions in MCSRStefan Roese2008-11-20-0/+4
| | | | | | | | | | | | | | | | This is needed on Canyonlands which still has an exception pending while running relocate_code(). This leads to a failure after trap_init() is moved to the top of board_init_r(). Signed-off-by: Stefan Roese <sr@denx.de>
* | AT91RM9200DK: fix broken boot from NOR flashWolfgang Denk2008-11-24-1/+1
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | at91rm9200: fix broken boot from nor flashJens Scharsig2008-11-24-4/+1
| | | | | | | | | | | | | | This patch fix the broken boot from NOR Flash on AT91RM9200 boards, if CONFIG_AT91RM9200 is defined and nor preloader is used. Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
* | AT91: Enable PLLB for USBStelian Pop2008-11-21-0/+18
|/ | | | | | | | | | | | | | | | | At least some (old ?) versions of the AT91Bootstrap do not set up the PLLB correctly to 48 MHz in order to make USB host function correctly. This patch sets up the PLLB to the same values Linux uses, and makes USB work ok on the following CPUs: - AT91CAP9 - AT91SAM9260 - AT91SAM9263 This patch also defines CONFIG_USB_STORAGE and CONFIG_CMD_FAT for all the relevant AT91CAP9/AT91SAM9 atmel boards. Signed-off-by: Stelian Pop <stelian@popies.net> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Align end of bss by 4 bytesSelvamuthukumar2008-11-18-1/+8
| | | | | | | | | | Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc86xxWolfgang Denk2008-11-18-111/+352
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| * mpc8641: Support 36-bit physical addressingBecky Bruce2008-11-10-11/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch creates a memory map with all the devices in 36-bit physical space, in addition to the 32-bit map. The CCSR relocation is moved (again, sorry) to allow for the physical address to be 36 bits - this requires translation to be enabled. With 36-bit physical addressing enabled, we are no longer running with VA=PA translations. This means we have to distinguish between the two in the config file. The existing region name is used to indicate the virtual address, and a _PHYS variety is created to represent the physical address. Large physical addressing is not enabled by default. Set CONFIG_PHYS_64BIT in the config file to turn this on. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * mpc8641: Change 32-bit memory mapBecky Bruce2008-11-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory map on the 8641hpcn is modified to look more like the 85xx boards; this is a step towards a more standardized layout going forward. As part of this change, we now relocate the flash. The regions for some of the mappings were far larger than they needed to be. I have reduced the mappings to match the actual sizes supported by the hardware. In addition I have removed the comments at the head of the BAT blocks in the config file, rather than updating them. These get horribly out of date, and it's a simple matter to look at the defines to see what they are set to since everything is right here in the same file. Documentation has been changed to reflect the new map, as this change is user visible, and affects the OS which runs post-uboot. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLYBecky Bruce2008-11-10-10/+10
| | | | | | | | | | | | | | | | | | | | | | We define CONFIG_MONITOR_BASE_EARLY to define the initial location of the bootpage in flash. Use this to create an early mapping definition for the FLASH, and change the early_bats code to use this. This change facilitates the relocation of the flash since the early mappings are no longer tied to the final location of the flash. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * mpc86xx: Use SRR0/1/rfi to enable address translation, not blrBecky Bruce2008-11-10-11/+8
| | | | | | | | | | | | | | | | | | | | Using a mtmsr/blr means that you have to be executing at the same virtual address once you enable translation. This is unnecessarily restrictive, and is not really how this is usually done. Change it to use the more common mtspr SRR0/SRR1 and rfi method. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * mpc86xx: Move setup_bats into cpu_init_fBecky Bruce2008-11-10-5/+4
| | | | | | | | | | | | | | | | | | | | | | In order to later allow for a physical relocation of the flash, setup_bats, which sets up the final BAT mapping for the board, needs to happen *after* init_laws(). Otherwise, there will be no window programmed for the flash at the new physical location at the point when we change the mmu translation. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * Merge commit 'wd/master'Jon Loeliger2008-11-10-286/+1166
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| * | powerpc: change 86xx SMP boot methodBecky Bruce2008-11-04-73/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | We put the bootpg for the secondary cpus into memory and use BPTR to get to it. This is a step towards converting to the ePAPR boot methodology. Also, the code is written to deal properly with more than 4GB of RAM. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * | powerpc 86xx: Handle CCSR relocation earlierBecky Bruce2008-11-03-5/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the CCSR gets relocated while translation is enabled, meaning we need 2 BAT translations to get to both the old location and the new location. Also, the DEFAULT CCSR location has a dependency on the BAT that maps the FLASH region. Moving the relocation removes this unnecessary dependency. This makes it easier and more intutive to modify the board's memory map. Swap BATs 3 and 4 on 8610 so that all 86xx boards use the same BAT for CCSR space. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* | | Moved initialization of PPC4xx EMAC to cpu_eth_init()Ben Warren2008-11-09-0/+14
| | | | | | | | | | | | | | | | | | | | | Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* | | Moved PPC4xx EMAC driver to drivers/netBen Warren2008-11-09-2128/+0
| | | | | | | | | | | | | | | | | | | | | Also changed path in all linker scripts that reference this driver Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* | | Changed PPC4xx EMAC driver to require CONFIG_PPC4xx_EMACBen Warren2008-11-09-9/+1
| | | | | | | | | | | | | | | | | | | | | All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* | | Moved initialization of MPC8XX SCC to cpu_eth_init()Ben Warren2008-11-09-0/+4
| | | | | | | | | | | | | | | | | | Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | | Moved initialization of MPC8220 FEC to cpu_eth_init()Ben Warren2008-11-09-0/+13
| | | | | | | | | | | | | | | | | | Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | | Moved initialization of QE Ethernet controller to cpu_eth_init()Ben Warren2008-11-09-1/+37
| | | | | | | | | | | | | | | | | | Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | | Moved initialization of FCC Ethernet controller to cpu_eth_initBen Warren2008-11-09-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards: Several MPC8xx boards Several MPC8260/MPC8272 boards Several MPC85xx boards Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | | Fix typo in cpu/mpc85xx/cpu.cBen Warren2008-11-09-1/+1
| | | | | | | | | | | | | | | | | | CONFIG_MPC85xx_FEC -> CONFIG_MPC85XX_FEC Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | | net: Move initialization of Au1x00 SoC ethernet MAC to cpu_eth_initShinya Kuribayashi2008-11-09-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch will move au1x00_eth_initialize from net/eth.c to cpu_eth_init as a part of ongoing eth_initialize cleanup work. The function ret value is also fixed as it should be negative on fail. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | | Moved initialization of IXP4XX_NPE Ethernet controller to cpu_eth_init()Ben Warren2008-11-09-0/+9
| |/ |/| | | | | | | | | Also, removed the driver initialization from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2008-11-09-15/+47
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| * | Change to use "do_div" macroTomohiro Masubuchi2008-11-04-13/+45
| | | | | | | | | | | | Signed-off-by: Tomohiro Masubuchi <tomohiro_masubuchi@tripeaks.co.jp>
| * | ARM926EJ-S: relocate OMAP specific 'cpuinfo.c' into OMAP directoryRoman Mashak2008-11-04-2/+2
| |/ | | | | | | | | | | | | OMAP identification is implemented in 'cpuinfo.c' and located in ARM926EJ-S directory. It makes sense to place this file in OMAP specific subdirectory, i.e. cpu/arm926ejs/omap Signed-off-by: Roman Mashak <romez777@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-coldfireWolfgang Denk2008-11-09-269/+1119
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| * | ColdFire: Fix compilation errorTsiChung Liew2008-11-03-9/+9
| | | | | | | | | | | | | | | | | | | | | The error was caused by the change for strmhz() in cpu.c. A few of them were one extra close parenthesis. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| * | ColdFire: Add MCF5301x CPU and M53017EVB supportTsiChung Liew2008-11-03-49/+304
| | | | | | | | | | | | Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| * | ColdFire: Add SBF support for M52277EVBTsiChung Liew2008-11-03-17/+541
| | | | | | | | | | | | | | | | | | Add serial boot support Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| * | ColdFire: Relocate FEC's GPIO and mii functions protocolsTsiChung Liew2008-11-03-3/+185
| | | | | | | | | | | | | | | | | | | | | Place FEC pin assignments in cpu_init.c from platform's mii.c Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| * | ColdFire: Modules header files cleanupTsiChung Liew2008-11-03-191/+80
| |/ | | | | | | | | | | | | | | | | | | | | | | Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG, MDHA, SKHA, INTC, and FlexBus structures and definitions in immap_5xxx.h to more unify modules header files. Append DSPI support for m547x_8x. SSI cleanup. Remove USB Host structure from immap_539.h. Apply changes to use FlexBus structures in mcf52x2's cpu_init.c and platform configuration files. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* | Consolidate MAX/MIN definitionsAndy Fleming2008-11-02-2/+0
|/ | | | | | | There were several, now there is one (two if you count the lower-case versions). Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2008-11-01-305/+128
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| * Blackfin: fix up UART status bit handlingMike Frysinger2008-10-23-12/+60
| | | | | | | | | | | | | | | | Some Blackfin UARTs are read-to-clear while others are write-to-clear. This can cause problems when we poll the LSR and then later try and handle any errors detected. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: small cpu init optimization while setting interrupt maskMike Frysinger2008-10-23-5/+2
| | | | | | | | | | | | | | Use the sti instruction to set the initial interrupt mask rather than banging on the core IMASK MMR to save both space and time. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: set initial stack correctly according to Blackfin ABIMike Frysinger2008-10-23-3/+3
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: make baud calculation more accurateMike Frysinger2008-10-23-4/+4
| | | | | | | | | | | | | | | | We should use the algorithm in the Linux kernel so that the UART divisor calculation is more accurate. It also fixes problems on some picky UARTs that have sampling anomalies. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: decode hwerrcause/excause when crashingMike Frysinger2008-10-23-2/+40
| | | | | | | | | | | | Having to decode hwerrcause/excause values is a pain, so automate it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: fix register dump messagesMike Frysinger2008-10-23-1/+5
| | | | | | | | | | | | Make sure we report RETI/IPEND correctly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: don't bother displaying reboot msg when crashingMike Frysinger2008-10-23-5/+1
| | | | | | | | | | | | | | The hang function already tells you to reboot, so no point in showing it twice. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: enable support for nested interruptsMike Frysinger2008-10-23-4/+10
| | | | | | | | | | | | | | During cpu init, make sure we initialize the CEC properly so that interrupts can fire and be handled while U-Boot is running. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: drop unused cache flush codeMike Frysinger2008-10-23-231/+1
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
generated by cgit v1.1 at 2024-12-26 16:41:31 +0000