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* Add QE brg freq and correct qe bus freq fdt update codeKim Phillips2008-01-09-1/+3
| | | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: add ability to upload QE firmwareTimur Tabi2008-01-09-0/+1
| | | | | | | | | | | Define the layout of a binary blob that contains a QE firmware and instructions on how to upload it. Add function qe_upload_firmware() to parse the blob and perform the actual upload. Add command-line command "qe fw" to take a firmware blob in memory and upload it. Update ft_cpu_setup() on 85xx to create the 'firmware' device tree node if U-Boot has uploaded a firmware. Fully define 'struct rsp' in immap_qe.h to include the actual RISC Special Registers. Signed-off-by: Timur Tabi <timur@freescale.com>
* 85xx: Remove cache config from configs.hKumar Gala2008-01-09-2/+7
| | | | | | | | | Either use the standard defines in asm/cache.h or grab the information at runtime from the L1CFG SPR. Also, minor cleanup in cache.h to make the code a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Reworked FSL Book-E TLB macros to be more readableKumar Gala2008-01-09-13/+10
| | | | | | | | | | | The old macros made it difficult to know what WIMGE and perm bits were set for a TLB entry. Actually use the bit masks for these items since they are only a single bit. Also moved the macros into mmu.h out of e500.h since they aren't specific to e500. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-usbWolfgang Denk2008-01-09-0/+16
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| * Merge git://www.denx.de/git/u-bootMarkus Klotzbuecher2008-01-09-2825/+5168
| |\ | | | | | | | | | | | | | | | Conflicts: board/tqm5200/tqm5200.c
| * | PXA USB OHCI: "usb stop" implementation.Rodolfo Giometti2007-10-31-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some USB keys need to be switched off before loading the kernel otherwise they can remain in an undefined status which prevents them to be correctly recognized by the kernel. Signed-off-by: Rodolfo Giometti <giometti@linux.it> Signed-off-by: Markus Klotzbuecher <mk@denx.de>
* | | fix various commentsMarcel Ziswiler2008-01-09-19/+19
| | | | | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* | | fix comments with new drivers organizationMarcel Ziswiler2008-01-09-1/+1
| | | | | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* | | Fix and optimize MII operations on FEC (MPC8xx) controllersGuennadi Liakhovetski2008-01-09-54/+53
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes several issues at least on a MPC885 based system with two FEC interfaces used in MII mode. 1. PHY discovery should first read PHY_PHYIDR2 register and only then PHY_PHYIDR1 like cpu/mpc8xx/fec.c::mii_discover_phy() does it, otherwise the values read are wrong. Also notice, that PHY discovery cannot work on MPC88x / MPC87x in setups with both FECs active at all in its present form, because for both interfaces the registers from FEC 1 are used to communicate over MII. 2. Remove code duplication for resetting the FEC by isolating it into a separate function. 3. Initialize MII on FEC 1 when communicating over FEC 2 in fec_init(). 4. Optimize mii_init() to only reset the FEC 1 controller once. 5. Fix a typo in mii_init() using index i instead of j thus potentially leading to unpredictable results. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
* | Coding Style clenaup; update CHANGELOGWolfgang Denk2008-01-09-2/+2
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | IXP: Add full baud-rate support for ixp42x, ixp45x and ixp46xJean-Christophe PLAGNIOL-VILLARD2008-01-09-14/+10
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xxWolfgang Denk2008-01-09-399/+320
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| * | mpc83xx: convert to using do_fixup_*()Kim Phillips2008-01-08-480/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | convert to using simpler mpc85xx style fdt update code; streamline by eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm the old school FLAT_TREE code from 83xx (since the sbc8349 was just converted over to using libfdt). Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | Add support CONFIG_UEC_ETH3 in MPC83xxJoakim Tjernlund2008-01-08-1/+115
| | | | | | | | | | | | Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
| * | mpc83xx: Add the support of MPC837xEMDS boardDave Liu2008-01-08-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC837xEMDS board support: * DDR2 400MHz hardcoded and SPD init * Local bus NOR Flash * I2C, UART, MII and RTC * eTSEC RGMII * PCI host Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | mpc83xx: Add the support of MPC8315E SoCDave Liu2008-01-08-3/+49
| | | | | | | | | | | | | | | | | | | | | The MPC8315E SoC including e300c3 core and new IP blocks, such as TDM, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | mpc83xx: Add the support of MPC837x SoCDave Liu2008-01-08-30/+161
| | | | | | | | | | | | | | | | | | | | | The MPC837x SoC including e300c4 core and new IP blocks, such as SDHC, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
* | | Merge branch 'lwmon5-no-ocm'Stefan Roese2008-01-09-1/+65
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| * | | ppc4xx: Add CFG_POST_ALT_WORD_ADDR to support non OCM POST WORD storageStefan Roese2008-01-09-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The privious 4xx POST implementation only supported storing the POST WORD in OCM. Since we need to reserve the OCM on LWMON5 for the logbuffer we need to store the POST WORD in some other non volatile location. This patch adds CFG_POST_ALT_WORD_ADDR to specify an address for such a location. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Add 44x cache locking to better support init-ram in d-cacheStefan Roese2008-01-09-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for locking the init-ram/stack in d-cache, so that other regions may use d-cache as well Note, that this current implementation locks exactly 4k of d-cache, so please make sure that you don't define a bigger init-ram area. Take a look at the lwmon5 440EPx implementation as a reference. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | ppc4xx: Move cpu/ppc4xx/vecnum.h into include pathMatthias Fuchs2008-01-09-408/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows the use of 4xx interrupt vector number defines in board specific code outside cpu/ppc4xx. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | | | ppc4xx: Fix UIC2 vector number baseMatthias Fuchs2008-01-09-16/+16
| | | | | | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | | | ppc4xx: Return 0 on success in 4xx ethernet driverStefan Roese2008-01-08-2/+3
| |/ / |/| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Remove weak binding from common Denali data-eye search codeLarry Johnson2008-01-05-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | Now that there are no board-specific versions of "denali_core_search_data_eye()", the weak binding on the common version can be removed. Signed-off-by: Larry Johnson <lrj@acm.org>
* | | Merge branch 'katmai-ddr-gda'Stefan Roese2008-01-05-59/+37
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| * | | ppc4xx: Remove unused CONFIG_ECC_ERROR_RESET from 44x_spd_ddr2.cStefan Roese2008-01-05-44/+0
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setupStefan Roese2008-01-05-15/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Katmai the complete auto-calibration somehow doesn't seem to produce the best results, meaning optimal values for RQFD/RFFD. This was discovered by GDA using a high bandwidth scope, analyzing the DDR2 signals. GDA provided a fixed value for RQFD, so now on Katmai "only" RFFD is auto-calibrated. This patch also adds RDCC calibration as mentioned on page 7 of the AMCC PowerPC440SP/SPe DDR2 application note: "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" Signed-off-by: Stefan Roese <sr@denx.de>
* | | | ppc4xx: Add functionality to GPIO supportLawrence R. Johnson2008-01-04-23/+40
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes two additions to GPIO support: First, it adds function gpio_read_in_bit() to read the a bit from the GPIO Input Register (GPIOx_IR) in the same way that function gpio_read_out_bit() reads a bit from the GPIO Output Register (GPIOx_OR). Second, it modifies function gpio_set_chip_configuration() to provide an additional option for configuring the GPIO from the "CFG_4xx_GPIO_TABLE". According to the 440EPx User's Manual, when an alternate output is used, the three-state control is configured in one of two ways, depending on the particular output. The first option is to select the corresponding alternate three-state control in the GPIOx_TRSH/L registers. The second option is to select the GPIO Three-State Control Register (GPIOx_TCR) in the GPIOx_TRSH/L registers, and set the corresponding bit in the GPIOx_TCR register to enable the output. For example, the Manual specifies configuring the GPIO00 Alternate 1 Signal (PreAddr07) to use the alternate three-state control (first option), and specifies configuring the GPIO32 Alternate 1 Signal (USB2OM0) with the output enabled in the GPIOx_TCR register (second option). Currently, gpio_set_chip_configuration() configures all alternate signal outputs to use the first option. This patch allow the second option to be selected by setting the "out_val" element in the table entry to "GPIO_OUT_1". The first option is used when the "out_val" element is set to "GPIO_OUT_0". Because "out_val" is not currently used when an alternate signal is selected, and because all current GPIO tables set "out_val" to "GPIO_OUT_0" for all alternate signals, this patch should not change any existing configurations. Signed-off-by: Larry Johnson <lrj@acm.org>
* | | Merge commit 'wd/master'Jon Loeliger2008-01-03-1844/+4559
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| * | ppc4xx: Enable 405EP PCI arbiter per default on all boardsStefan Roese2007-12-28-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In an attmemt to clean up the 4xx start.S file, I removed the enabling of the internal 405EP PCI arbiter. This is needed for multiple other 405EP platforms, like most of the esd 405EP. Now the internal PCI arbiter is enabled again per default as it has been before. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * | ppc4xx: Fix bug in cpu_init.c (405EP instead of 450EP)Stefan Roese2007-12-28-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * | Merge branch 'master' of /home/stefan/git/u-boot/u-boot into for-1.3.2-ver2Stefan Roese2007-12-27-259/+739
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| | * \ Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2007-12-27-4/+1
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| | | * | TQM885D: Exchanged SDRAM timing by a more relaxed timing.Jens Gehrlein2007-12-27-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CAS-Latency=2, Write Recovery Time tWR=2 The max. supported bus frequency is 66 MHz. Therefore, changed threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz. Signed-off-by: Martin Krause <martin.krause@tqs.de>
| | * | | Fix coding style issues; update CHANGELOG.Wolfgang Denk2007-12-27-44/+40
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2007-12-27-0/+529
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| | | * | Merge branch 'master' of git://www.denx.de/git/u-boot-shWolfgang Denk2007-12-27-0/+529
| | | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: MAINTAINERS Signed-off-by: Wolfgang Denk <wd@denx.de>
| | | | * \ Merge git://www.denx.de/git/u-bootNobuhiro Iwamatsu2007-12-07-61/+17
| | | | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/Makefile
| | | | * \ \ Merge git://www.denx.de/git/u-bootNobuhiro Iwamatsu2007-11-29-341/+392
| | | | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/Makefile
| | | | * | | | sh: Update core code of SuperH.Nobuhiro Iwamatsu2007-09-23-22/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | | * | | | Merge git://www.denx.de/git/u-bootNobuhiro Iwamatsu2007-09-23-5470/+14939
| | | | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: CREDITS
| | | | * | | | | sh: First support code of SuperH.Nobuhiro Iwamatsu2007-05-13-0/+399
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * | | | | | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2007-12-27-7/+15
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| | | * | | | | | Merge branch 'master' of git://www.denx.de/git/u-boot-avr32Wolfgang Denk2007-12-27-7/+15
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| | | | * | | | | | AVR32: Fix wrong pin setup for USART3Haavard Skinnemoen2007-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported by Gerhard Berghofer: in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18 instead of PB18 and PB19. which is obviously correct. There's currently no code that uses USART3, but custom boards may run into problems. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| | | | * | | | | | AVR32: Make some AT32AP700x peripherals optionalHaavard Skinnemoen2007-12-17-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a chip-features file providing definitions of the form AT32AP700x_CHIP_HAS_<peripheral> to indicate the availability of the given peripheral on the currently selected chip. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| | | | * | | | | | AVR32: Rename at32ap7000 -> at32ap700xHaavard Skinnemoen2007-12-17-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SoC-specific code for all the AT32AP700x CPUs is practically identical; the only difference is that some chips have less features than others. By doing this rename, we can add support for the AP7000 derivatives simply by making some features conditional. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| | | | * | | | | | atmel_mci: Show SR when block read failsHaavard Skinnemoen2007-12-17-6/+7
| | | | | |_|_|/ / | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Show controller status as well as card status when an error occurs during block read. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| | * | | | | | | Handle Asynchronous DDR clock on 85xxKumar Gala2007-12-11-4/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8572 introduces the concept of an asynchronous DDR clock with regards to the platform clock. Introduce get_ddr_freq() to report the DDR freq regardless of sync/async mode. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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