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* Add support for Freescale M5271: Merge with /work/u-boot.mcf5271Marian Balakowicz2006-04-27-4/+144
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| * Add support for Freescale M5271 processorZachary P. Landau2006-01-26-4/+144
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* | MPC5200: enable snooping of DMA transactions on XLB even if no PCIWolfgang Denk2006-04-18-4/+4
| | | | | | | | | | is configured; othrwise DMA accesses aren't cache coherent which causes for example USB to fail.
* | Some code cleanupWolfgang Denk2006-04-16-111/+111
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* | Fix Lite500B support: Merge with /home/raj/git/u-boot.l5200b_pciWolfgang Denk2006-04-06-5/+5
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| * | Set SDelay register in the DDR controller for the MPC5200B chip.Rafal Jaworowski2006-03-29-5/+5
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* | | Merge with /home/sr/git/u-boot/4xx-sdramWolfgang Denk2006-04-05-34/+342
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| * | | Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)Stefan Roese2006-03-31-34/+342
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 405 SDRAM: - The SDRAM parameters can now be defined in the board config file and the 405 SDRAM controller values will be calculated upon bootup (see PPChameleonEVB). When those settings are not defined in the board config file, the register setup will be as it is now, so this implementation should not break any current design using this code. Thanks to Andrea Marson from DAVE for this patch. 440 DDR: - Added function sdram_tr1_set to auto calculate the TR1 value for the DDR. - Added ECC support (see p3p440). Patch by Stefan Roese, 17 Mar 2006
* | | Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.SWolfgang Denk2006-04-03-1/+2
| | | | | | | | | | | | Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473]
* | | GCC-4.x fixes: clean up global data pointer initialization for all boards.Wolfgang Denk2006-03-31-233/+195
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* | | Merge with http://www.denx.de/git/u-boot.gitMarkus Klotzbuecher2006-03-24-453/+4384
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| * | Add support for MPC859/866 Rev. A.0Wolfgang Denk2006-03-18-3/+8
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| * | Support for DDR with 32-data path. Addotional notes on injectingRafal Jaworowski2006-03-16-12/+49
| | | | | | | | | | | | multiple-bit errors.
| * | Add support for ECC DDR initialization on MPC83xx.Marian Balakowicz2006-03-14-22/+108
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| * | Add DMA support for MPC83xx.Marian Balakowicz2006-03-14-0/+85
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| * | Add sync in do_reset() routine for MPC83xx after RPR registerMarian Balakowicz2006-03-14-0/+2
| | | | | | | | | | | | | | | was written to. It is need on some targets when BAT translation is enabled.
| * | Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.Marian Balakowicz2006-03-14-0/+34
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| * | Correct shift offsets in icache_status and dcache_status for MPC83xx.Marian Balakowicz2006-03-14-2/+2
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| * | Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific timer andWolfgang Denk2006-03-13-167/+531
| | | | | | | | | | | | | | | cpu_reset code from cpu/$(CPU) into the new cpu/$(CPU)/$(SOC) directories Patch by Andreas Engel, 13 Mar 2006
| * | Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.cStefan Roese2006-03-13-1/+1
| | | | | | | | | | | | Patch by Stefan Roese, 13 Mar 2006
| * | cpu/ppc4xx/start.S : exceptions are enabled after relocationStefan Roese2006-03-13-23/+18
| | | | | | | | | | | | Patch by Cedric Vincent, 6 June 2005
| * | au1x00_eth.c: check malloc return value and abort if it failedWolfgang Denk2006-03-13-2/+6
| | | | | | | | | | | | Patch by Andrew Dyer, 26 Jul 2005
| * | Fix bug in [id]cache_status commands for MPC85xx processors;Wolfgang Denk2006-03-13-2/+2
| | | | | | | | | | | | | | | | | | should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005
| * | Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#mpc83xxWolfgang Denk2006-03-12-209/+349
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| | * | Enable address translation on MPC83xxKumar Gala2006-02-10-179/+298
| | | | | | | | | | | | | | | | Patch by Kumar Gala, 10 Feb 2006
| | * | Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xxKumar Gala2006-01-25-28/+21
| | | | | | | | | | | | | | | | Patch by Kumar Gala, 25 Jan 2006
| | * | Only disable the MPC83xx watchdog if its enabled out of reset.Kumar Gala2006-01-11-0/+6
| | | | | | | | | | | | | | | | | | | | If its disabled out of reset SW can later enable it if so desired Patch by Kumar Gala, 11 Jan 2006
| | * | Allow config of GPIO direction & data registers at boot on 83xxKumar Gala2006-01-11-0/+8
| | | | | | | | | | | | | | | | Patch by Kumar Gala, 11 Jan 2006
| | * | Enable time handling on 83xxKumar Gala2006-01-11-0/+10
| | | | | | | | | | | | | | | | Patch by Kumar Gala, 11 Jan 2006
| | * | Make System IO Config Registers board configurable on MPC83xxKumar Gala2006-01-11-2/+6
| | |/ | | | | | | | | | Patch by Kumar Gala, 11 Jan 2006
| * | Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#ft_infrWolfgang Denk2006-03-12-0/+38
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| | * | Add helper function for generic flat device tree fixups for mpc83xxKumar Gala2006-01-11-0/+38
| | |/ | | | | | | | | | Patch by Kumar Gala 11 Jan 2006
| * | Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280ECWolfgang Denk2006-03-12-8/+19
| | | | | | | | | | | | Patch by KokHow Teh, 16 Jun 2005
| * | Coding Style cleanupWolfgang Denk2006-03-12-171/+165
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| * | Add missing Blackfin files.Wolfgang Denk2006-03-12-0/+3135
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| * | More GCC 4.x woesWolfgang Denk2006-03-11-1/+2
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| * | Some code cleanup for GCC 4.xWolfgang Denk2006-03-11-2/+2
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* | | Added config options CFG_MONAHANS_RUN_MODE_OSC_RATIO andMarkus Klotzbuecher2006-03-24-2/+15
| | | | | | | | | | | | | | | CFG_MONAHANS_TURBO_RUN_MODE_RATIO for configuring the Monahans core frequency.
* | | delta board: DA9030 initialization and i2c support. Some minor changes toMarkus Klotzbuecher2006-03-24-5/+14
|/ / | | | | | | make the pxa i2c driver work with the monahans cpu.
* | Cleanup (get rid of debug code that sneaked in)Wolfgang Denk2006-03-07-1/+0
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* | Merge with /home/wd/git/u-boot/masterWolfgang Denk2006-03-06-48/+42
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| * | Initial port to MCC200 board (work in progress)Wolfgang Denk2006-02-22-1/+2
| | | | | | | | | | | | Minimally modified patch by Bluetechnix, Vienna
* | | Cleanup of NAND support of delta board using the Monahans Data FlashMarkus Klotzbücher2006-03-06-1/+9
| | | | | | | | | | | | Controller.
* | | Lots of new stuff:Markus Klotzbücher2006-03-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Debug message can be turned on and off. * Waiting for events now times out. * Implemented RESET command. * Added appropriate nand_bbt_descriptor and nand_oobinfo. Remaining Problems: * Read Status still behaves weird an returns invalid stuff sometimes. * ECC Placement does not respect our scheme in nand_oobinfo.
* | | All subsystem clocks not immediately need are turned at reset.Markus Klotzbücher2006-02-28-0/+10
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* | | Added GPIO initialization of DF signal. Still not working.Markus Klotzbücher2006-02-28-0/+1
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* | | This is the first commit for the u-boot zylonite port. The following has beMarkus Klotzbücher2006-02-07-12/+47
|/ / | | | | | | | | | | | | | | | | | | | | | | | | done so far: * created zylonite board dir (based on lubbock) * extended some - but not all pxa sources and headers for Intel Monahans support (CONFIG_CPU_MONAHANS) * created Makefile zylonite target + MAKEALL entry * added some debug nonsense, remove later, grep for mk@tbd Status: compiles (eldk-4.0), and can be started with BDI, but runs forever and doesn't halt at breakpoints. Hmmm...
* | PMC405 and CPCI405: Moved configuration of pci resources into config file.Stefan Roese2006-01-18-4/+5
|/ | | | | | PMC405 and CPCI2DP: Added firmware download and booting via pci. Patch by Matthias Fuchs, 20 Dec 2005
* MPC5200: Set PCI retry counter to 0 = infinite retry;Wolfgang Denk2005-12-16-1/+5
| | | | | The default of 255 is too short for slow devices. Patch by Martin Nykodym, 12 Dec 2005
* (no commit message)Wolfgang Denk2005-12-12-1/+1
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