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* AT91SAM9: Move CONFIG_HAS_DATAFLASH to MakefileJean-Christophe PLAGNIOL-VILLARD2008-04-01-7/+7
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Port AT91CAP9 to the new headersStelian Pop2008-04-01-56/+100
| | | | | | Adapt the existing AT91CAP9 code to the new headers and APIs. Signed-off-by: Stelian Pop <stelian@popies.net>
* Move at91cap9 specific files to at91sam9 directoryStelian Pop2008-04-01-8/+5
| | | | | | | | | AT91CAP9 and AT91SAM9 SoCs are very close hardware wise, so a common infrastructure can be used. Let this infrastructure be named after the AT91SAM9 family, and move the existing AT91CAP9 files to the new place. Signed-off-by: Stelian Pop <stelian@popies.net>
* Use timer_init() instead of board supplied interrupt_init()Stelian Pop2008-04-01-2/+2
| | | | | | | The timer on AT91CAP9/AT91SAM9 is supplied by the SoC, and not by the board, so use timer_init() instead of interrupt_init(). Signed-off-by: Stelian Pop <stelian@popies.net>
* use correct at91rm9200 register nameDavid Brownell2008-03-30-3/+3
| | | | | | | | This fixes a naming bug for at91rm9200 lowlevel init code: NOR boot flash is on chipselect 0, not chipselect 2. This makes code use the register name from chip datasheets. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* 85xx: Add cpu_mp_lmb_reserve helper to reserve boot pageKumar Gala2008-03-26-0/+15
| | | | | | | Provide a board_lmb_reserve helper function to ensure we reserve the page of memory we are using for the boot page translation code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Update multicore boot mechanism to ePAPR v0.81 specKumar Gala2008-03-26-64/+115
| | | | | | | | | | | | The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix merge duplicationKumar Gala2008-03-26-49/+0
| | | | | | ft_fixup_cpu() got duplicated in some merge snafu. Remove the duplicate. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Speed up get_ddr_freq() and get_bus_freq()James Yang2008-03-26-16/+5
| | | | | | | | | | get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were called. However, get_sys_info() recalculates extraneous information when called each time. Have get_ddr_freq() and get_bus_freq() return memoized values from global_data instead. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Show DDR memory data rate in addition to the memory clock frequency.James Yang2008-03-26-3/+6
| | | | | | | | | Show the DDR memory data rate in addition to the memory clock frequency. For DDR/DDR2 memories the memory data rate is 2x the memory clock. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: get_tbclk() speed up and rounding fixJames Yang2008-03-26-5/+3
| | | | | | | | | | Speed up get_tbclk() by referencing pre-computed bus clock frequency value from global data instead of sys_info_t. Fix rounding of result to nearest; previously it was rounding upwards. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update SVR numbers to expand supportAndy Fleming2008-03-26-38/+49
| | | | | | | | | | | | | FSL has taken to using SVR[16:23] as an SOC sub-version field. This is used to distinguish certain variants within an SOC family. To account for this, we add the SVR_SOC_VER() macro, and update the SVR_* constants to reflect the larger value. We also add SVR numbers for all of the current variants. Finally, to make things neater, rather than use an enormous switch statement to print out the CPU type, we create and array of SVR/name pairs (using a macro), and print out the CPU name that matches the SVR SOC version. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Added support for multicore boot mechanismKumar Gala2008-03-26-0/+49
| | | | | | | | | | Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Added support for multicore boot mechanismKumar Gala2008-03-26-0/+405
| | | | | | | | | Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add the concept of CFG_CCSRBAR_PHYSKumar Gala2008-03-26-3/+3
| | | | | | | | | When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'new-image' of git://www.denx.de/git/u-boot-testingBartlomiej Sieka2008-03-26-2/+2
|\ | | | | | | | | | | | | | | | | Conflicts: common/cmd_bootm.c cpu/mpc8xx/cpu.c Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
| * Merge branch 'master' of git://www.denx.de/git/u-boot into new-imageMarian Balakowicz2008-03-12-17/+44
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| * \ Merge branch 'master' of git://www.denx.de/git/u-boot into new-imageMarian Balakowicz2008-02-29-86/+72
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| * | | [new uImage] Pull in libfdt if CONFIG_FIT is enabledMarian Balakowicz2008-02-21-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New uImage format (Flattened Image Tree) requires libfdt functionality, print out error message if CONFIG_OF_LIBFDT is not defined. New uImage support is enabled by defining CONFIG_FIT (and CONFIG_OF_LIBFDT). This commit turns it on by default. Signed-off-by: Marian Balakowicz <m8@semihalf.com>
* | | | mpc83xx: add "fsl,soc" and "fsl,immr" compatible fixupsAnton Vorontsov2008-03-25-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | device_type = "soc" is being deprecated, newer device trees will use "fsl,soc" and/or "fsl,immr" for the soc nodes. This patch also adds clock-frequency property for soc nodes (the same value as bus-frequency). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | | | 83xx: serdes setup routinesAnton Vorontsov2008-03-25-0/+146
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | | | 83xx: split COBJS onto separate linesAnton Vorontsov2008-03-25-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | ..plus get rid of some #ifdefs in the .c files. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | | | mpc8323erdb: Improve the system performanceMichael Barkowski2008-03-25-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are based on kernel UCC ethernet performance: 1. Make the CSB bus pipeline depth as 4, and enable the repeat mode 2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT switch to enable this setting. The following changes are based on the App Note AN3369 and verified to improve memory latency using LMbench: 3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0 4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting previously. 5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on Twr=15ns, and this was already the setting in DDR_MODE) 6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on Trp=15ns) 7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on Tras=40ns) 8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on Trcd=15ns) 9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on Trfc=75ns) 10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based on Tfaw=50ns) 11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based on CL=3 and WL=2). Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* | | | Coding Style cleanyp; update CHANGELOGWolfgang Denk2008-03-26-2/+0
| | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-mipsWolfgang Denk2008-03-26-106/+186
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| * | | | [MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kBShinya Kuribayashi2008-03-25-5/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * | | | [MIPS] Fix dcache_status()Shinya Kuribayashi2008-03-25-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | You can't judge UNCACHED by Config.K0 LSB. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * | | | [MIPS] Introduce _machine_restartShinya Kuribayashi2008-03-25-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Handles machine specific functions by using weak functions. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * | | | [MIPS] Cleanup CP0 Status initializationShinya Kuribayashi2008-03-25-9/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add setup_c0_status from Linux. For the moment we disable interrupts, set CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for reset-time configuration and will work well across most processors. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * | | | [MIPS] Initialize CP0 Cause before setting up CP0 Status registerShinya Kuribayashi2008-03-25-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this change, we'll be suffering from deffered WATCH exception once Status.EXL is cleared. Make sure Cause.WP is cleared. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * | | | [MIPS] INCA-IP: Move watchdog init code from start.S to lowlevel_init()Shinya Kuribayashi2008-03-25-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move things to appropriate place. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * | | | [MIPS] Implement flush_cache()Shinya Kuribayashi2008-03-25-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We do Hit_Writeback_Inv_D and Hit_Invalidate_I. You might think that you don't need to do Hit_Invalidate_I, but flush_cache() needs it since this function is used not only in U-Boot specfic programs but also at loading target binaries. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * | | | [MIPS] Fix I-/D-cache initialization loopsShinya Kuribayashi2008-03-25-39/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I again per a loop for I-cache initialization. But according to 'See MIPS Run', we're encouraged to use three separate loops rather than combining them *for both I- and D-cache*. This patch tries to fix this. In accordance with fixing above, mips_init_[id]cache are separated from mips_cache_reset(), and rewrite cache loops are completely rewritten with useful macros. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * | | | [MIPS] Replace memory clearance code with f_fill64Shinya Kuribayashi2008-03-25-15/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This routine fills memory with zero by 64 bytes, and is 64-bit capable. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * | | | [MIPS] cpu/mips/cache.S: Introduce NESTED/LEAF/END macrosShinya Kuribayashi2008-03-25-18/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch replaces the current function definitions with NESTED, LEAF and END macro. They specify some more additional information about the function; an alignment of symbol, type of symbol, stack frame usage, etc. These information explicitly tells the assembler and the debugger about the types of code we want to generate. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * | | | [MIPS] Request for the 'mips_cache_lock()' removalShinya Kuribayashi2008-03-25-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial intension of having mips_cache_lock() was to use the cache as memory for temporary stack use so that a C environment can be set up as early as possible. But now mips_cache_lock() follow lowlevel_init(). We've already have the real memory initilaized at this point, therefore we could/should use it. No reason to lock at all. Other problems: Cache locking is not consistent across MIPS implementaions. Some imple- mentations don't support locking at all. The style of locking varies - some support per line locking, others per way, etc. Some parts use bits in status registers instead of cache ops. Current mips_cache_lock() is not necessarily general-purpose. And this is worthy of special mention; once U-Boot/MIPS locks the lines, they are never get unlocked, so the code relies on whatever gets loaded after U-Boot to re-initialize the cache and clear the locks. We're sup- posed to have CFG_INIT_RAM_LOCK and unlock_ram_in_cache() implemented, but leave the situation as it is for a long time. For these reasons, I proposed the removal of mips_cache_lock() from the global start-up code. This patch adds CFG_INIT_RAM_LOCK_MIPS to make existing users aware that *things have changed*. If he wants the same behavior as before, he needs to have CFG_INIT_RAM_LOCK_MIPS in his config file. If we don't have any regression report through several releases, then we'll remove codes entirely. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Acked-by: Andrew Dyer <amdyer@gmail.com>
* | | | | MPC5200: support setup without FECAndré Schwarz2008-03-25-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include FEC specific nodes in ft_cpu_setup only if CONFIG_MPC5xxx_FEC is defined. Systems without FEC, i.e. no FEC node in DTB, should be possible. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: Grant Likely <grant.likely@secretlab.ca>
* | | | | 8xx: Update OF support on 8xxBryan O'Donoghue2008-03-25-12/+72
|/ / / / | | | | | | | | | | | | | | | | | | | | This patch does some shifting around of OF support on 8xx. Signed-off-by: Bryan O'Donoghue <bodonoghue@codehermit.ie>
* | | | LWMON5: POST RTC fixYuri Tikhonov2008-03-20-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the RTC API to provide one a status for the time reported by the rtc_get() function: 0 - a reliable time is guaranteed, < 0 - a reliable time isn't guaranteed (power fault, clock issues, and so on). The RTC chip drivers are responsible for providing this info if the corresponding chip supports such functionality. If not - always report that the time is reliable. The POST RTC test was modified to detect the RTC faults utilizing this new rtc_get() feature. Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* | | | ppc4xx: Add Canyonlands NAND booting supportStefan Roese2008-03-15-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 460EX doesn't support a fixed bootstrap option to boot from 512 byte page NAND devices. The only bootstrap option for NAND booting is option F for 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap EEPROM needs to be programmed accordingly. This patch adds basic NAND booting support for the AMCC Canyonlands aval board and also adds support to the "bootstrap" command, to enable NAND booting I2C setting. Tested with 512 byte page NAND device (32MByte) on Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | ppc4xx: Add basic support for AMCC 460EX/460GT (2/5)Stefan Roese2008-03-15-7/+178
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the AMCC 460EX/460GT PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | ppc4xx: Add basic support for AMCC 460EX/460GT (1/5)Stefan Roese2008-03-15-93/+553
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the AMCC 460EX/460GT PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | ppc4xx: interrupt.c reworkedStefan Roese2008-03-15-448/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is a rework of the 4xx interrupt handling done while adding the 460EX/GT support. Interrupts are needed on 4xx for the EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | ppc4xx: program_tlb now uses 64bit physical addessStefan Roese2008-03-15-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the physical addess parameter from 32bit to 64bit. This is needed for 36bit 4xx platforms to access areas located beyond the 4GB border, like SoC peripherals (EBC etc.). Signed-off-by: Stefan Roese <sr@denx.de>
* | | | ppc4xx: miiphy.c reworkedStefan Roese2008-03-15-116/+80
| |_|/ |/| | | | | | | | | | | | | | | | | While adding the 460EX/GT support I reworked the 4xx miiphy code. It badly neede some cleanup. Signed-off-by: Stefan Roese <sr@denx.de>
* | | PPC4xx (Sequoia): Fix Ethernet "remote fault" problemsMike Nuss2008-03-04-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Every now and then a Sequoia board (or equivalent hardware) had problems connecting to a Gigabit capable network interface. There were differences in the PHY setup between Linux and U-Boot. This patch fixes the problem. Apparently "remote fault" is being set, which signals to some devices (on the other end of the cable) that a fault has occurred, while other devices ignore it. I believe the RF bit was causing the issue, but I removed T4 also, to match up with Linux. Signed-off-by: Mike Nuss <mike@terascala.com>
* | | ppc4xx: EMAC: Fix 405EZ fifo size setup in EMAC_MR1Stefan Roese2008-03-02-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The 405EZ only supports 512 bytes of rx-/tx-fifo EMAC sizes. But currently 4k/2k is configured. This patch fixes this issue. Thanks to Thomas Kindler <tkindler@lenord.de> for pointing this out. Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxWolfgang Denk2008-03-02-6/+14
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| * | | 85xx: Don't icbi when unlocking the cacheKumar Gala2008-02-27-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no reason to icbi when invalidating the temporary stack in the d-cache. Its impossible on e500 to have the i-cache contain any addresses in the temp stack and it can be problematic in generating transactions on the bus to non-valid addresses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | Fix source for ECM error IVPRAndy Fleming2008-02-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The source vector for the ECM was being set to 2, but that's what the source vector for DDR was being set to. Change it to 1. Signed-off-by: Andy Fleming <afleming@freescale.com>
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